CD54HC107F3A
ActiveHIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE TRIGGER J-K FLIP-FLOPS WITH RESET
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CD54HC107F3A
ActiveHIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE TRIGGER J-K FLIP-FLOPS WITH RESET
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Technical Specifications
Parameters and characteristics for this part
| Specification | CD54HC107F3A |
|---|---|
| Clock Frequency | 60 MHz |
| Current - Output High, Low [custom] | 5.2 mA |
| Current - Output High, Low [custom] | 5.2 mA |
| Current - Quiescent (Iq) | 4 çA |
| Function | Reset |
| Input Capacitance | 10 pF |
| Max Propagation Delay @ V, Max CL | 29 ns |
| Mounting Type | Through Hole |
| Number of Bits per Element | 1 |
| Number of Elements | 2 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Output Type | Complementary |
| Package / Case | 14-CDIP |
| Supplier Device Package | 14-CDIP |
| Trigger Type | Negative Edge |
| Type | JK Type |
| Voltage - Supply [Max] | 6 V |
| Voltage - Supply [Min] | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Texas Instruments | TUBE | 1 | $ 17.41 | |
| 100 | $ 15.21 | |||
| 250 | $ 11.72 | |||
| 1000 | $ 10.49 | |||
Description
General part information
5962-8515401 Series
The ’HC107 and ’HCT107 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.
These flip-flops have independent J, K, Reset and Clock inputs and Q and Q\ outputs. They change state on the negative-going transition of the clock pulse. Reset is accomplished asynchronously by a low level input.
This device is functionally identical to the HC/HCT73 but differs in terminal assignment and in some parametric limits.
Documents
Technical documentation and resources