5962-9583201Q2A

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Texas Instruments

3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

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DocumentsAdvanced Bus Interface Logic Selection Guide LOGIC Pocket Data Book (Rev. B)+15

5962-9583201Q2A

Active

Texas Instruments

3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

Deep-Dive with AI

DocumentsAdvanced Bus Interface Logic Selection Guide LOGIC Pocket Data Book (Rev. B)+15

Specifications Pricing Series Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	5962-9583201Q2A

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5962-9583201 Series

3.3-V ABT Octal Edge-Triggered D-type Flip-Flops With 3-State Outputs

Part	Mounting Type	Trigger Type	Max Propagation Delay @ V, Max CL	Function	Operating Temperature [Max]	Operating Temperature [Min]	Number of Bits per Element	Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Input Capacitance	Number of Elements	Current - Quiescent (Iq)	Supplier Device Package	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Package / Case	Clock Frequency	Output Type
Texas Instruments SNJ54LVTH574W	Surface Mount	Positive Edge	4.9 ns	Standard	125 °C	-55 °C	8	D-Type	2.7 V	3.6 V	3 pF	1	190 çA	20-CFP	24 mA	48 mA	20-CFlatPack	150 MHz	Non-Inverted Tri-State
Texas Instruments 5962-9583201Q2A

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Bulk	8	$ 42.20
Texas Instruments	TUBE	1	$ 51.40
		100	$ 45.69
		250	$ 37.56
		1000	$ 33.60

Description

General part information

5962-9583201 Series

These octal flip-flops are designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment.

The eight flip-flops of the ’LVTH574 devices are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.

A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.