
UC28023NG4
ObsoleteCURRENT MODE PWM CONTROLLER 1.5A 1000KHZ 16-PIN PDIP TUBE
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UC28023NG4
ObsoleteCURRENT MODE PWM CONTROLLER 1.5A 1000KHZ 16-PIN PDIP TUBE
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Technical Specifications
Parameters and characteristics for this part
| Specification | UC28023NG4 |
|---|---|
| Clock Sync | False |
| Control Features | Frequency Control, Soft Start, Enable, Current Limit, Ramp |
| Duty Cycle (Max) [Max] | 90 % |
| Frequency - Switching [Max] | 460 kHz |
| Frequency - Switching [Min] | 340 kHz |
| Function | Step-Up, Step-Up/Step-Down |
| Mounting Type | Through Hole |
| Number of Outputs | 1 |
| Operating Temperature [Max] | 105 °C |
| Operating Temperature [Min] | -40 °C |
| Output Configuration | Positive |
| Output Phases | 1 |
| Output Type | Transistor Driver |
| Package / Case | 0.3 in |
| Package / Case | 16-DIP |
| Package / Case | 7.62 mm |
| Supplier Device Package | 16-PDIP |
| Synchronous Rectifier | True |
| Topology | Forward Converter, Full-Bridge, Flyback, Half-Bridge, Boost, Push-Pull |
| Voltage - Supply (Vcc/Vdd) [Max] | 30 V |
| Voltage - Supply (Vcc/Vdd) [Min] | 9 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
Description
General part information
UC28023 Series
The UC28023 and UC28025 are fixed-frequency PWM controllers optimized for high-frequency switched-mode power-supply applications. The UC28023 is a single output PWM for single-ended topologies while the UC28025 offers dual alternating outputs for double-ended and full bridge topologies.
Targeted for cost-effective solutions with minimal external components. UC2802x devices include an oscillator, a temperature compensated reference, a wide bandwidth error amplifier, a high-speed current-sense comparator, and high-current, active-high, totem-pole outputs to directly drive external MOSFETs.
Protection circuitry includes a current limit comparator with a 1-V threshold, a TTL compatible shutdown port, and a soft-start pin which doubles as a maximum duty-cycle clamp. The logic is fully latched to provide jitter-free operation and prohibit multiple pulses at an output. An undervoltage lockout section with 800 mV of hysteresis assures low start-up current. During undervoltage lockout, the outputs are high impedance. Propagation delays through the comparators and logic circuitry have been minimized while maximizing bandwidth and slew rate of the error amplifier.
Documents
Technical documentation and resources
No documents available