71V2546S100PFG
Obsolete3.3V 128KX36 ZBT SYNCHRONOUS PIPELINED SRAM WITH 2.5V I/O
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71V2546S100PFG
Obsolete3.3V 128KX36 ZBT SYNCHRONOUS PIPELINED SRAM WITH 2.5V I/O
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Technical Specifications
Parameters and characteristics for this part
| Specification | 71V2546S100PFG |
|---|---|
| Access Time | 5 ns |
| Clock Frequency | 100 MHz |
| Memory Format | SRAM |
| Memory Interface | Parallel |
| Memory Organization | 128K x 36 |
| Memory Size | 4.5 Mbit |
| Memory Type | Volatile |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 70 °C |
| Operating Temperature [Min] | 0 °C |
| Package / Case | 100-LQFP |
| Supplier Device Package | 100-TQFP (14x14) |
| Technology | SRAM - Synchronous, SDR (ZBT) |
| Voltage - Supply [Max] | 3.465 V |
| Voltage - Supply [Min] | 3.135 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Bulk | 47 | $ 6.49 | |
| Tray | 1 | $ 9.01 | ||
| 10 | $ 8.30 | |||
| 25 | $ 8.12 | |||
| 72 | $ 8.09 | |||
Description
General part information
71V2546 Series
The 71V2546 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2546 has an on-chip burst counter. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.
Documents
Technical documentation and resources