These 4-bit registers feature parallel inputs, parallel outputs, J-Kserial inputs, shift/load control input, and a direct overriding clear. The registers have two modes of operation: parallel (broadside) load, and shift (in the direction QAand QD).

Parallel loading is accomplished by applying the 4-bits of data and taking the shift/load control input low. The data is loaded into the associated flip-flop and appears at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited.

Shifting is accomplished synchronously when the shift/load control input is high. Serial data for this mode is entered at the J-Kinputs. These inputs permit the first stage to perform as a J-K, D, or T type flip-flop as shown in the function table.Read more