71V3557S80PFGI
Active3.3V 128KX36 ZBT SYNCHRONOUS FLOW-THROUGH SRAM WITH 3.3V I/O
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71V3557S80PFGI
Active3.3V 128KX36 ZBT SYNCHRONOUS FLOW-THROUGH SRAM WITH 3.3V I/O
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | 71V3557S80PFGI |
|---|---|
| Access Time | 8 ns |
| Memory Format | SRAM |
| Memory Interface | Parallel |
| Memory Organization | 128K x 36 |
| Memory Size | 4.5 Mbit |
| Memory Type | Volatile |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 100-LQFP |
| Supplier Device Package | 100-TQFP (14x14) |
| Technology | SRAM - Synchronous, SDR (ZBT) |
| Voltage - Supply [Max] | 3.465 V |
| Voltage - Supply [Min] | 3.135 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tray | 1 | $ 10.68 | |
| 10 | $ 9.89 | |||
| 25 | $ 9.66 | |||
| 72 | $ 9.61 | |||
| 144 | $ 8.46 | |||
| 288 | $ 8.04 | |||
| 504 | $ 7.96 | |||
| 1008 | $ 7.70 | |||
Description
General part information
71V3557 Series
The 71V3557 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V3557 contains address, data-in and control signal registers. The outputs are flow-through (no output data register).
Documents
Technical documentation and resources