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574MLFT - 574 - Block Diagram

574MLFT

Obsolete
Renesas Electronics Corporation

ZERO DELAY, LOW SKEW BUFFER

Deep-Dive with AI

Search across all available documentation for this part.

574MLFT - 574 - Block Diagram

574MLFT

Obsolete
Renesas Electronics Corporation

ZERO DELAY, LOW SKEW BUFFER

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

Specification574MLFT
Differential - Input:OutputFalse
Divider/MultiplierNo
Divider/MultiplierYes
Frequency - Max [Max]160 MHz
InputCMOS
Mounting TypeSurface Mount
Number of Circuits1
Operating Temperature [Max]70 °C
Operating Temperature [Min]0 °C
OutputCMOS
Package / Case8-SOIC
Package / Case [x]0.154 in
Package / Case [y]3.9 mm
PLLTrue
Ratio - Input:Output1:4
Supplier Device Package8-SOIC
TypeZero Delay Buffer, Fanout Buffer (Distribution)
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 17.87
10$ 12.89
25$ 11.61
100$ 10.19
250$ 9.50
500$ 9.08
1000$ 9.07
Digi-Reel® 1$ 17.87
10$ 12.89
25$ 11.61
100$ 10.19
250$ 9.50
500$ 9.08
1000$ 9.07
Tape & Reel (TR) 3000$ 9.39

Description

General part information

574M Series

The 574 is a low jitter, low-skew, high performance PLL-based zero delay buffer for high speed applications. Based on IDT's proprietary low jitter Phase Locked Loop (PLL) techniques, the device provides four low skew outputs at speeds up to 160 MHz at 3.3 V. When one of the outputs is connected directly to FBIN, the rising edge of each output is aligned with the rising edge of the input clock. External delay elements connected in the feedback loops will cause the outputs to occur before the inputs by the amount of propagation delay of the external element.

Documents

Technical documentation and resources