574MILF

Obsolete

Renesas Electronics Corporation

ZERO DELAY, LOW SKEW BUFFER

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Search across all available documentation for this part.

DocumentsDatasheet 574 Datasheet

574MILF

Obsolete

Renesas Electronics Corporation

ZERO DELAY, LOW SKEW BUFFER

Deep-Dive with AI

DocumentsDatasheet 574 Datasheet

Specifications Pricing Series Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	574MILF

Differential - Input:Output	False
Divider/Multiplier	False
Frequency - Max [Max]	160 MHz
Input	CMOS
Mounting Type	Surface Mount
Number of Circuits	1
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output	CMOS
Package / Case	8-SOIC
Package / Case [x]	0.154 in
Package / Case [y]	3.9 mm
PLL	True
Ratio - Input:Output	1:4
Supplier Device Package	8-SOIC
Type	Zero Delay Buffer, Fanout Buffer (Distribution)
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	3 V

574M Series

Zero Delay, Low Skew Buffer

Part	Operating Temperature [Max]	Operating Temperature [Min]	Input	Mounting Type	Output	Differential - Input:Output	Ratio - Input:Output	Divider/Multiplier	Divider/Multiplier	Voltage - Supply [Max]	Voltage - Supply [Min]	Number of Circuits	Type	PLL	Frequency - Max [Max]	Supplier Device Package	Package / Case	Package / Case [y]	Package / Case [x]	Divider/Multiplier
Renesas Electronics Corporation 574MLFT	70 °C	0 °C	CMOS	Surface Mount	CMOS		1:4	No	Yes	5.5 V	3 V	1	Fanout Buffer (Distribution) Zero Delay Buffer		160 MHz	8-SOIC	8-SOIC	3.9 mm	0.154 in
Renesas Electronics Corporation 574MILF	85 °C	-40 °C	CMOS	Surface Mount	CMOS		1:4			5.5 V	3 V	1	Fanout Buffer (Distribution) Zero Delay Buffer		160 MHz	8-SOIC	8-SOIC	3.9 mm	0.154 in

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Description

General part information

574M Series

The 574 is a low jitter, low-skew, high performance PLL-based zero delay buffer for high speed applications. Based on IDT's proprietary low jitter Phase Locked Loop (PLL) techniques, the device provides four low skew outputs at speeds up to 160 MHz at 3.3 V. When one of the outputs is connected directly to FBIN, the rising edge of each output is aligned with the rising edge of the input clock. External delay elements connected in the feedback loops will cause the outputs to occur before the inputs by the amount of propagation delay of the external element.