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74ACT11074N - 14-Dip

74ACT11074N

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Texas Instruments

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

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74ACT11074N - 14-Dip

74ACT11074N

Active
Texas Instruments

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

Technical Specifications

Parameters and characteristics for this part

Specification74ACT11074N
Clock Frequency125 MHz
Current - Output High, Low24 mA
Current - Quiescent (Iq)4 çA
FunctionReset, Set(Preset)
Input Capacitance3.5 pF
Max Propagation Delay @ V, Max CL8.5 ns
Mounting TypeThrough Hole
Number of Bits per Element1
Number of Elements2
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Output TypeComplementary
Package / Case14-DIP
Package / Case [x]0.3 "
Package / Case [y]7.62 mm
Trigger TypePositive Edge
TypeD-Type
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]4.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
ArrowN/A 25$ 1.44
DigikeyTube 1$ 1.99
10$ 1.79
25$ 1.69
100$ 1.44
250$ 1.35
500$ 1.19
Texas InstrumentsTUBE 1$ 2.77
100$ 2.29
250$ 1.65
1000$ 1.24

Description

General part information

74ACT11074 Series

This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset () or clear () input sets or resets the outputs regardless of the levels of the other inputs. Whenandare inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the D input may be changed without affecting the levels at the outputs.

The 74ACT11074 is characterized for operation from -40°C to 85°C.

This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset () or clear () input sets or resets the outputs regardless of the levels of the other inputs. Whenandare inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the D input may be changed without affecting the levels at the outputs.