66AK2E05XABDA25

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Texas Instruments

HIGH PERFORMANCE MULTICORE DSP+ARM - 4X ARM A15 CORES, 1X C66X DSP CORE, NETCP, 10GBE

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Search across all available documentation for this part.

DocumentsDatasheet General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide +69

66AK2E05XABDA25

Active

Texas Instruments

HIGH PERFORMANCE MULTICORE DSP+ARM - 4X ARM A15 CORES, 1X C66X DSP CORE, NETCP, 10GBE

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DocumentsDatasheet General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide +69

Specifications Pricing Series Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	66AK2E05XABDA25

Clock Rate	1.25 GHz
Interface	MDIO, DMA, I2C, USIM, USB 3.0, EBI/EMI, TSIP, Ethernet, SPI, PCIe, UART/USART
Mounting Type	Surface Mount
Non-Volatile Memory	256 kB
On-Chip RAM	2 MB
Operating Temperature [Max]	100 °C
Operating Temperature [Min]	-40 °C
Package / Case	1089-BFBGA, FCBGA
Supplier Device Package	1089-FCBGA (27x27)
Type	DSP+ARM®
Voltage - Core	Variable
Voltage - I/O	1.5 V, 1.35 V, 3.3 V, 1.8 V

66AK2E05 Series

High performance multicore DSP+Arm - 4x Arm A15 cores, 1x C66x DSP core, NetCP, 10GbE

Part	Clock Rate	Operating Temperature [Min]	Operating Temperature [Max]	Interface	Supplier Device Package	Type	Mounting Type	On-Chip RAM	Package / Case	Voltage - Core	Non-Volatile Memory	Voltage - I/O
Texas Instruments 66AK2E05XABDA25	1.25 GHz	-40 °C	100 °C	DMA EBI/EMI Ethernet I2C MDIO PCIe SPI TSIP UART/USART USB 3.0 USIM	1089-FCBGA (27x27)	DSP+ARM®	Surface Mount	2 MB	1089-BFBGA FCBGA	Variable	256 kB	1.35 V 1.5 V 1.8 V 3.3 V
Texas Instruments 66AK2E05XABD25	1.25 GHz	0 °C	85 °C	DMA EBI/EMI Ethernet I2C MDIO PCIe SPI TSIP UART/USART USB 3.0 USIM	1089-FCBGA (27x27)	DSP+ARM®	Surface Mount	2 MB	1089-BFBGA FCBGA	Variable	256 kB	1.35 V 1.5 V 1.8 V 3.3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tray	40	$ 204.29
Texas Instruments	JEDEC TRAY (5+1)	1	$ 176.42
		100	$ 159.69
		250	$ 155.13
		1000	$ 152.08

Description

General part information

66AK2E05 Series

The 66AK2E0x is a high performance device based on TI’s KeyStone II Multicore SoC Architecture, incorporating the most performance-optimized Cortex-A15 processor single-core or quad-core CorePac and C66x DSP core, that can run at a core speed of up to 1.4 GHz. TI’s 66AK2E0x device enables a high performance, power-efficient and easy to use platform for developers of a broad range of applications such as enterprise grade networking end equipment, data center networking, avionics and defense, medical imaging, test and automation.

TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (for example, ARM CorePac (Cortex-A15 Processor Quad Core CorePac), C66x CorePac, network processing, and uses a queue-based communication system that allows the device resources to operate efficiently and seamlessly. This unique device architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to high-speed IO, to each operate at maximum efficiency with no blocking or stalling.

TI’s C66x core launches a new era of DSP technology by combining fixed-point and floating point computational capability in the processor without sacrificing speed, size, or power consumption. The raw computational performance is an industry-leading 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz operating frequency). It can execute 8 single precision floating point MAC operations per cycle and can perform double- and mixed-precision operations and is IEEE754 compliant. For fixed-point use, the C66x core has 4× the multiply accumulate (MAC) capability of C64×+ cores. The C66x CorePac incorporates 90 new instructions targeted for floating point and vector math oriented processing. These enhancements yield sizeable performance improvements in popular DSP kernels used in signal processing, mathematical, and image acquisition functions. The C66x core is backwards code compatible with TI'’s previous generation C6000 fixed and floating point DSP cores, ensuring software portability and shortened software development cycles for applications migrating to faster hardware.

Documents

Technical documentation and resources

66AK2E05XABDA25

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66AK2E05XABDA25

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Technical Specifications

66AK2E05 Series

Pricing

Description

66AK2E05 Series

Documents

Datasheet

General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide

Software and Hardware Design Challenges Due to Dynamic Raw NAND Market

Save power and costs with TI's K2E on-chip networking features

C66x DSP Cache User's Guide

Debug and Trace for KeyStone II Devices User's Guide

10 Gigabit Ethernet Switch Subsystem User Guide for KeyStone II Devices

PCIe Use Cases for KeyStone Devices

Power Management of KS2 Device (Rev. C)

Making your search SIMPLE, even when your ideas are complex

Using Arm ROM Bootloader on Keystone II Devices

PCI Express (PCIe) for KeyStone Devices User's Guide (Rev. D)

KeyStone™-II-based processors: 10G Ethernet as an optical interface

Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide

Keystone II DDR3 Initialization

66AK2Ex KeyStone Multicore DSP+ARM(R) System-on-Chips (Rev. A)

HyperLink for KeyStone Devices User's Guide (Rev. C)

Video Infrastructure - Applications of the K2E, K2H platforms

Clocking Spreadsheet for K2E Device Family

POWERLINK on TI Sitara Processors (Rev. A)

Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H)

DSP Bootloader for KeyStone Architecture User's Guide (Rev. C)

Keystone Error Detection and Correction EDC ECC (Rev. A)

Multicore Programming Guide (Rev. B)

Processing solutions for biometric systems

Telecom Serial Interface Port (TSIP) for KeyStone Devices User's Guide

External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A)

Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I)

Serializer/Deserializer (SerDes) for KeyStone II Devices User Guide (Rev. A)

KeyStone II DDR3 interface bring-up

64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A)

Quality of service on Keystone II architecture

ARM Bootloader User Guide for KeyStone II Devices

66AK2E05/02 KeyStone SoC Silicon Errata (Silicon Rev 1.0) (Rev. B)

ARM Optimizing C/C++ Compiler v5.2 User's Guide (Rev. J)

KeyStone II Architecture Universal Serial Bus 3.0 (USB 3.0) (Rev. A)

C66x CPU and Instruction Set Reference Guide

Throughput Performance Guide for KeyStone II Devices (Rev. B)

DDR3 Design Requirements for KeyStone Devices (Rev. D)

ARM Assembly Language Tools v5.2 User's Guide (Rev. M)

Industrial Imaging: Applications of the K2H and K2E platforms

Packet Accelerator 2 (PA2) for K2E and K2L Devices User's Guide

TI DSP Benchmarking

C66x CorePac User's Guide (Rev. C)

Introduction to TMS320C6000 DSP Optimization

Security Accelerator 2 (SA2) for K2E and K2L Devices User's Guide

Multicore Shared Memory Controller (MSMC) User Guide for KeyStone II Devices

How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A)

Optimizing Loops on the C66x DSP

Hardware Design Guide for KeyStone II Devices

Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B)

ARM CorePac User Guide for KeyStone II Devices

Keystone Multicore Device Family Schematic Checklist

DDR3 Memory Controller for KeyStone II Devices User's Guide (Rev. C)

Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices UG

Processor SDK RTOS Audio Benchmark Starter Kit

Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A)

Clocking Design Guide for KeyStone Devices

PCI Express (PCIe) Resource Wiki for Keystone Devices (Rev. A)

The Case for 10G Ethernet in Embedded Processing

SERDES Link Commissioning on KeyStone I and II Devices

Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A)

Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C)

Keystone II DDR3 Debug Guide

Power Consumption Summary for K2E System-on-Chip (SoC) Device Family

Thermal Design Guide for DSP and Arm Application Processors (Rev. B)

Differentiating AM5K2E02 and AM5K2E04 SoCs from Alternate ARM® Cortex®-A15 Devic

Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A)

66AK2E05/02 Multicore DSP+ARM KeyStone II System-on-Chip (SoC) datasheet (Rev. D)

Network Coprocessor (NETCP) for K2E and K2L Devices User's Guide