674R-01LFT

Obsolete

Renesas Electronics Corporation

DUAL-CHANNEL LVCMOS CLOCK DIVIDER

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Search across all available documentation for this part.

DocumentsDatasheet 674-01 Datasheet

674R-01LFT

Obsolete

Renesas Electronics Corporation

DUAL-CHANNEL LVCMOS CLOCK DIVIDER

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DocumentsDatasheet 674-01 Datasheet

Specifications Pricing Series Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	674R-01LFT

Differential - Input:Output	False
Divider/Multiplier	Yes/No
Frequency - Max [Max]	235 MHz
Input	Clock
Mounting Type	Surface Mount
Number of Circuits	1
Operating Temperature [Max]	70 °C
Operating Temperature [Min]	0 °C
Output	Clock
Package / Case	28-SSOP
PLL	False
Ratio - Input:Output [custom]	2:2
Type	Clock Divider
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	3 V

674-01 Series

Dual-channel LVCMOS Clock Divider

Part	Divider/Multiplier	Mounting Type	Frequency - Max [Max]	Number of Circuits	Voltage - Supply [Max]	Voltage - Supply [Min]	PLL	Type	Operating Temperature [Max]	Operating Temperature [Min]	Differential - Input:Output	Input	Output	Package / Case	Ratio - Input:Output [custom]
Renesas Electronics Corporation 674R-01LF	Yes/No	Surface Mount	235 MHz	1	5.5 V	3 V		Clock Divider	70 °C	0 °C		Clock	Clock	28-SSOP	2:2
Renesas Electronics Corporation 674R-01LFT	Yes/No	Surface Mount	235 MHz	1	5.5 V	3 V		Clock Divider	70 °C	0 °C		Clock	Clock	28-SSOP	2:2

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Description

General part information

674-01 Series

The 674-01 consists of two separate configurable dividers. The A Divider is a 7-bit divider and can divide by 3 to 129. The B Divider consists of a 9-bit divider followed by a post divider. The 9-bit divider can divide by 12 to 519. The post divider has eight settings of 1, 2, 4, 5, 6, 7, 8, and 10; giving a maximum total divide of 5190. The A and B Dividers can be cascaded to give a maximum divide of 669510. The 674-01 supports the 673 PLL Building Block and enables the user to build a full custom PLL synthesizer.