674R-01LF
ObsoleteDUAL-CHANNEL LVCMOS CLOCK DIVIDER
Deep-Dive with AI
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674R-01LF
ObsoleteDUAL-CHANNEL LVCMOS CLOCK DIVIDER
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | 674R-01LF |
|---|---|
| Differential - Input:Output | False |
| Divider/Multiplier | Yes/No |
| Frequency - Max [Max] | 235 MHz |
| Input | Clock |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 70 °C |
| Operating Temperature [Min] | 0 °C |
| Output | Clock |
| Package / Case | 28-SSOP |
| PLL | False |
| Ratio - Input:Output [custom] | 2:2 |
| Type | Clock Divider |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tube | 150 | $ 4.34 | |
Description
General part information
674-01 Series
The 674-01 consists of two separate configurable dividers. The A Divider is a 7-bit divider and can divide by 3 to 129. The B Divider consists of a 9-bit divider followed by a post divider. The 9-bit divider can divide by 12 to 519. The post divider has eight settings of 1, 2, 4, 5, 6, 7, 8, and 10; giving a maximum total divide of 5190. The A and B Dividers can be cascaded to give a maximum divide of 669510. The 674-01 supports the 673 PLL Building Block and enables the user to build a full custom PLL synthesizer.
Documents
Technical documentation and resources