SN54LS674J
Active16-BIT SHIFT REGISTERS 24-CDIP -
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SN54LS674J
Active16-BIT SHIFT REGISTERS 24-CDIP -
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Technical Specifications
Parameters and characteristics for this part
| Specification | SN54LS674J |
|---|---|
| Function | Serial to Parallel, Serial |
| Logic Type | Shift Register |
| Mounting Type | Through Hole |
| Number of Bits per Element | 16 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Output Type | Tri-State |
| Package / Case | 15.24 mm |
| Package / Case | 0.6 in |
| Package / Case | 24-CDIP |
| Supplier Device Package | 24-CDIP |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 4.5 V |
5962-8860701 Series
16-Bit Shift Registers
| Part | Logic Type | Package / Case | Package / Case | Package / Case | Number of Elements | Voltage - Supply [Min] | Voltage - Supply [Max] | Number of Bits per Element | Mounting Type | Output Type | Function | Supplier Device Package | Operating Temperature [Max] | Operating Temperature [Min] |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments | ||||||||||||||
Texas Instruments | Shift Register | 15.24 mm | 0.6 in | 24-CDIP | 1 | 4.5 V | 5.5 V | 16 | Through Hole | Tri-State | Serial to Parallel Serial | 24-CDIP | 125 °C | -55 °C |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Texas Instruments | TUBE | 1 | $ 38.42 | |
| 100 | $ 34.15 | |||
| 250 | $ 28.07 | |||
| 1000 | $ 25.11 | |||
Description
General part information
5962-8860701 Series
SN54LS673, SN74LS673
The 'LS673 is a 16-bit shift register and a 16-bit storage register in a single 24-pin package. A three-state input/output (SER/Q15) port to the shift register allows serial entry and/or reading of data. The storage register is connected in a parallel data loop with the shift register and may be asynchronously cleared by taking the store-clear input low. The storage register may be parallel loaded with shift-register data to provide shift-register status via the parallel outputs. The shift register can be parallel loaded with the storage-register data upon commmand.
A high logic level at the chip-level (CS\) input disables both the shift-register clock and the storage register clock and places SER/Q15 in the high-impedance state. The store-clear function is not disabled by the chip select.
Documents
Technical documentation and resources