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UCC21520ADWR - 16-SOIC

UCC21520ADWR

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Texas Instruments

5.7KVRMS 4A/6A DUAL-CHANNEL ISOLATED GATE DRIVER WITH DUAL INPUT AND DISABLE PIN IN DW PACKAGE

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UCC21520ADWR - 16-SOIC

UCC21520ADWR

Active
Texas Instruments

5.7KVRMS 4A/6A DUAL-CHANNEL ISOLATED GATE DRIVER WITH DUAL INPUT AND DISABLE PIN IN DW PACKAGE

Technical Specifications

Parameters and characteristics for this part

SpecificationUCC21520ADWR
Approval AgencyCQC, CSA, VDE, UR
Common Mode Transient Immunity (Min) [Min]100 V/ns
Current - Output High, Low4 A, 6 A
Mounting TypeSurface Mount
Number of Channels [custom]2
Operating Temperature [Max]125 °C
Operating Temperature [Min]-40 °C
Package / Case16-SOIC
Package / Case [x]0.295 in
Package / Case [y]7.5 mm
Propagation Delay tpLH / tpHL (Max) [Max]30 ns
Pulse Width Distortion (Max) [Max]6 ns
Rise / Fall Time (Typ) [custom]7 ns
Rise / Fall Time (Typ) [custom]6 ns
Supplier Device Package16-SOIC
TechnologyCapacitive Coupling
Voltage - Isolation5700 Vrms
Voltage - Output Supply [Max]25 V
Voltage - Output Supply [Min]6.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 4.36
10$ 3.92
25$ 3.70
100$ 3.21
250$ 3.05
500$ 2.73
1000$ 2.30
Digi-Reel® 1$ 4.36
10$ 3.92
25$ 3.70
100$ 3.21
250$ 3.05
500$ 2.73
1000$ 2.30
Tape & Reel (TR) 2000$ 2.04
Texas InstrumentsLARGE T&R 1$ 3.29
100$ 2.88
250$ 2.02
1000$ 1.63

Description

General part information

UCC21520-Q1 Series

The UCC21520 is an isolated dual-channel gate driver with 4A source and 6A sink peak current. It is designed to drive power MOSFETs, IGBTs, and SiC MOSFETs up to 5MHz.

The input side is isolated from the two output drivers by a 5.7kVRMS reinforced isolation barrier, with a minimum of 125V/ns common-mode transient immunity (CMTI). Internal functional isolation between the two secondary-side drivers allows a working voltage of up to 1500VDC.

Every driver can be configured as two low-side drivers, two high-side drivers, or a half-bridge driver with programmable dead time (DT). A disable pin shuts down both outputs simultaneously when it is set high, and allows normal operation when left open or grounded. As a fail-safe measure, primary-side logic failures force both outputs low.

Documents

Technical documentation and resources

Don't forget the gate driver: it’s the muscle

Technical article

External Gate Resistor Selection Guide (Rev. A)

Application brief

UL Certification E181974 Vol 4. Sec 7 (Rev. C)

Certificate

UCC215xx CQC Certificate of Product Certification

Certificate

The Use and Benefits of Ferrite Beads in Gate Drive Circuits

Application brief

Staying cool, efficiently

Technical article

For efficiencies’ sake – how to integrate bidirectional power flow (part 2)

Technical article

Impact of an isolated gate driver (Rev. A)

White paper

Why is the cloud isolated?

Technical article

Cities grow smarter through innovative semiconductor technologies

White paper

Pile on to a charger – my EV needs power

Technical article

UCC21520 CQC Certificate of Product Certification (Rev. A)

Certificate

Making a solar inverter more reliable than the sun

Technical article

Driving the future of HEV/EV with high-voltage solutions (Rev. B)

White paper

Impact of Narrow Pulse Widths in Gate Driver Circuits (Rev. A)

Application note

For efficiencies’ sake – how to integrate bidirectional power flow into your UPS design (part 1)

Technical article

UCC21520, a Universal Isolated Gate Driver with Fast Dynamic Response (Rev. A)

Application note

CSA Product Certificate (Rev. A)

Certificate

How to reduce system cost in a three-phase IGBT-based inverter design

Technical article

UCC21520, UCC21520A 4A, 6A, 5.7kVRMS Isolated Dual-Channel Gate Drivers datasheet (Rev. F)

Data sheet

VDE Certificate for Reinforced Isolation for DIN EN IEC 60747-17 (Rev. W)

Certificate

Using the UCC21520EVM-286, UCC21521CEVM-286, and UCC21530EVM286 User's Guide (Rev. C)

EVM User's guide

Understanding failure modes in isolators (Rev. B)

White paper

Understanding Peak IOH and IOL Currents (Rev. A)

Application brief