
71V65603S150BQGI8
Active3.3V 256K X 36 ZBT SYNCHRONOUS 3.3V I/O PIPELINED SRAM
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71V65603S150BQGI8
Active3.3V 256K X 36 ZBT SYNCHRONOUS 3.3V I/O PIPELINED SRAM
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | 71V65603S150BQGI8 |
|---|---|
| Access Time | 3.8 ns |
| Clock Frequency | 150 MHz |
| Memory Format | SRAM |
| Memory Interface | Parallel |
| Memory Organization [custom] | 36 |
| Memory Organization [custom] | 256 K |
| Memory Size | 9 Mbit |
| Memory Type | Volatile |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 165-TBGA |
| Supplier Device Package | 165-CABGA (13x15) |
| Technology | SRAM - Synchronous, SDR (ZBT) |
| Voltage - Supply [Max] | 3.465 V |
| Voltage - Supply [Min] | 3.135 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tape & Reel (TR) | 2000 | $ 22.02 | |
Description
General part information
71V65603 Series
The 71V65603 3.3V CMOS SRAM, organized as 256K X 36, is designed to eliminate dead bus cycles when turning the bus around between reads and writes or writes and reads. Thus, it has been given the name ZBT™, or Zero Bus Turnaround. The 71V65603 contains data I/O, address, and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.
Documents
Technical documentation and resources