Catalog
PCI Express® (PCIe®) to PCI bus translation bridge
Key Features
• Full ×1 PCI Express™ ThroughputFully Compliant WithPCI Express to PCI/PCI-X Bridge Specification, Revision 1.0Fully Compliant WithPCI Express Base Specification, Revision 2.0Fully Compliant WithPCI Local Bus Specification, Revision 2.3PCI Express Advanced Error Reporting Capability Including ECRC SupportSupport for D1, D2, D3hot, and D3coldActive-State Link Power Management Saves Power When Packet Activity on the PCI Express Link is Idle, Using Both L0s and L1 StatesWake Event and Beacon SupportError Forwarding Including PCI Express Data Poisoning and PCI Bus Parity ErrorsUses 100-MHz Differential PCI Express Common Reference Clock or 125-MHz Single-Ended, Reference ClockOptional Spread Spectrum Reference Clock is SupportedRobust Pipeline Architecture to Minimize Transaction LatencyFull PCI Local Bus 66-MHz/32-Bit ThroughputSupport for Six Subordinate PCI Bus Masters with Internal Configurable, 2-Level Prioritization SchemeInternal PCI Arbiter Supporting Up to 6 External PCI MastersAdvanced PCI Express Message Signaled Interrupt Generation for Serial IRQ InterruptsExternal PCI Bus Arbiter OptionPCI BusLOCKSupportJTAG/BS for Production TestPCI-ExpressCLKREQSupportClock Run and Power Override SupportSix Buffered PCI Clock Outputs (25 MHz, 33 MHz, 50 MHz, or 66 MHz)PCI Bus Interface 3.3-V and 5.0-V (25 MHz or 33 MHz only at 5.0 V) Tolerance OptionsIntegrated AUX Power Switch Drains VAUXPower Only When Main Power Is OffFive 3.3-V, Multifunction, General-Purpose I/O TerminalsMemory-Mapped EEPROM Serial-Bus Controller Supporting PCI Express Power Budget/Limit Extensions for Add-In CardsCompact Footprint, Lead-Free 144-Ball, ZAJ nFBGA, Lead-Free 169-Ball ZWS nFBGA, and PowerPad™ HTQFP 128-Pin PNP PackageFull ×1 PCI Express™ ThroughputFully Compliant WithPCI Express to PCI/PCI-X Bridge Specification, Revision 1.0Fully Compliant WithPCI Express Base Specification, Revision 2.0Fully Compliant WithPCI Local Bus Specification, Revision 2.3PCI Express Advanced Error Reporting Capability Including ECRC SupportSupport for D1, D2, D3hot, and D3coldActive-State Link Power Management Saves Power When Packet Activity on the PCI Express Link is Idle, Using Both L0s and L1 StatesWake Event and Beacon SupportError Forwarding Including PCI Express Data Poisoning and PCI Bus Parity ErrorsUses 100-MHz Differential PCI Express Common Reference Clock or 125-MHz Single-Ended, Reference ClockOptional Spread Spectrum Reference Clock is SupportedRobust Pipeline Architecture to Minimize Transaction LatencyFull PCI Local Bus 66-MHz/32-Bit ThroughputSupport for Six Subordinate PCI Bus Masters with Internal Configurable, 2-Level Prioritization SchemeInternal PCI Arbiter Supporting Up to 6 External PCI MastersAdvanced PCI Express Message Signaled Interrupt Generation for Serial IRQ InterruptsExternal PCI Bus Arbiter OptionPCI BusLOCKSupportJTAG/BS for Production TestPCI-ExpressCLKREQSupportClock Run and Power Override SupportSix Buffered PCI Clock Outputs (25 MHz, 33 MHz, 50 MHz, or 66 MHz)PCI Bus Interface 3.3-V and 5.0-V (25 MHz or 33 MHz only at 5.0 V) Tolerance OptionsIntegrated AUX Power Switch Drains VAUXPower Only When Main Power Is OffFive 3.3-V, Multifunction, General-Purpose I/O TerminalsMemory-Mapped EEPROM Serial-Bus Controller Supporting PCI Express Power Budget/Limit Extensions for Add-In CardsCompact Footprint, Lead-Free 144-Ball, ZAJ nFBGA, Lead-Free 169-Ball ZWS nFBGA, and PowerPad™ HTQFP 128-Pin PNP Package
Description
AI
The XIO2001 is a single-function PCI Express to PCI translation bridge that is fully compliant to thePCI Express to PCI/PCI-X Bridge Specification, Revision 1.0. For downstream traffic, the bridge simultaneously supports up to eight posted and four non-posted transactions. For upstream traffic, up to six posted and four non-posted transactions are simultaneously supported.
The PCI Express interface is fully compliant to thePCI Express Base Specification, Revision 2.0.
The PCI Express interface supports a ×1 link operating at full 250 MB/s packet throughput in each direction simultaneously. Also, the bridge supports the advanced error reporting including extended CRC (ECRC) as defined in thePCI Express Base Specification. Supplemental firmware or software is required to fully use both of these features.
The XIO2001 is a single-function PCI Express to PCI translation bridge that is fully compliant to thePCI Express to PCI/PCI-X Bridge Specification, Revision 1.0. For downstream traffic, the bridge simultaneously supports up to eight posted and four non-posted transactions. For upstream traffic, up to six posted and four non-posted transactions are simultaneously supported.
The PCI Express interface is fully compliant to thePCI Express Base Specification, Revision 2.0.
The PCI Express interface supports a ×1 link operating at full 250 MB/s packet throughput in each direction simultaneously. Also, the bridge supports the advanced error reporting including extended CRC (ECRC) as defined in thePCI Express Base Specification. Supplemental firmware or software is required to fully use both of these features.