XIO3130 Series

Integrated PCI Express® (PCIe) 1:3 4-port 4-lane packet switch

Catalog

Integrated PCI Express® (PCIe) 1:3 4-port 4-lane packet switch

Part	Package / Case	Voltage - Supply	Supplier Device Package	Interface	Applications	Mounting Type	Voltage - Supply [Min]	Voltage - Supply [Max]
Texas Instruments XIO3130ZHC	196-LBGA	1.5 V 3.3 V	196-BGA MICROSTAR (15x15)	PCI	PC's PDA's	Surface Mount
Texas Instruments XIO3130INMH	196-LBGA		196-NFBGA (15x15)	PCI Express	PCI-to-PCI Bridge	Surface Mount	1.35 V 3 V	1.65 V 3.6 V
Texas Instruments XIO3130IZHC	196-LBGA	1.5 V 3.3 V	196-BGA MICROSTAR (15x15)	PCI	PC's PDA's	Surface Mount

Catalog

Integrated PCI Express® (PCIe) 1:3 4-port 4-lane packet switch

Key Features

• PCI Express Base Specification, Revision 1.1PCI Express Card Electromechanical Specification, Revision 1.1PCI-to-PCI Bridge Architecture Specification, Revision 1.1PCI Bus Power Management Interface Specification, Revision 1.2PCI Express Fanout Switch With One ×1 Upstream Port andThree ×1 Downstream PortsPacket Transmission Starts While Reception Still in Progress (Cut-Through)256-Byte Maximum Data Payload SizePeer-to-Peer SupportWake Event and Beacon SupportSupport for D1, D2, D3hot, and D3coldActive State Power Management (ASPM) Using Both L0s and L1Low-Power PCI Express Transmitter ModeIntegrated AUX Power Switch Drains VAUX Power Only When Main Power Is OffIntegrated PCI Hot Plug SupportIntegrated REFCLK Buffers for Switch Downstream Ports3.3-V Multifunction I/O Pins for PCI Hot Plug Status and Controlor General Purpose I/OsOptional Serial EEPROM for System-Specific Configuration RegisterInitializationPCI Express, PCI Hot Plug are trademarks of others.PCI Express Base Specification, Revision 1.1PCI Express Card Electromechanical Specification, Revision 1.1PCI-to-PCI Bridge Architecture Specification, Revision 1.1PCI Bus Power Management Interface Specification, Revision 1.2PCI Express Fanout Switch With One ×1 Upstream Port andThree ×1 Downstream PortsPacket Transmission Starts While Reception Still in Progress (Cut-Through)256-Byte Maximum Data Payload SizePeer-to-Peer SupportWake Event and Beacon SupportSupport for D1, D2, D3hot, and D3coldActive State Power Management (ASPM) Using Both L0s and L1Low-Power PCI Express Transmitter ModeIntegrated AUX Power Switch Drains VAUX Power Only When Main Power Is OffIntegrated PCI Hot Plug SupportIntegrated REFCLK Buffers for Switch Downstream Ports3.3-V Multifunction I/O Pins for PCI Hot Plug Status and Controlor General Purpose I/OsOptional Serial EEPROM for System-Specific Configuration RegisterInitializationPCI Express, PCI Hot Plug are trademarks of others.

Description

The Texas Instruments XIO3130 switch is a PCI Express ×1 3-port fanout switch. The XIO3130 provides a single ×1 upstream port supporting full 250-MB/s packet throughput in each direction simultaneously. Three independently configurable ×1 downstream ports are provided that also support full 250-MB/s packet throughput in each direction simultaneously. A cut-through architecture is implemented to reduce the latency associated with packets moving through the PCI Express fabric. As soon as the address or routing information is decoded within the header of a packet entering an ingress port, the packet is directed to the egress port for forwarding. Packet poisoning using the EDB framing signal is supported in circumstances where packet errors are detected after the transmission of the egress packet begins. The downstream ports may be configured to support PCI Hot Plug slot implementations. In this scenario, the system designer may decide to use the integrated PCI Hot Plug-compliant controller. This feature is available through the classic PCI configuration space under the PCI Express Capability Structure. When enabled, the downstream ports provide the PCI Hot Plug standard mechanism to apply and remove power to the slot or socket. Power-management features include Active State Power Management, PME mechanisms, the Beacon/Wake protocol, and all conventional PCI D-states. When ASPM is enabled, each link automatically saves power when idle using the L0s and L1 states. PME messages are supported along with the PME_Turn_Off/PME_TO_Ack protocol. When enabled, the upstream port supports Beacon transmission as well as theWAKEside band signal to wake the system as the result of a PCI Hot Plug event. Furthermore, the downstream ports may be configured to detect Beacon from downstream devices and forward this upstream. The switch also supports the translation and forwarding ofWAKEfrom a downstream device into Beacon on the upstream port for cabled implementations. The Texas Instruments XIO3130 switch is a PCI Express ×1 3-port fanout switch. The XIO3130 provides a single ×1 upstream port supporting full 250-MB/s packet throughput in each direction simultaneously. Three independently configurable ×1 downstream ports are provided that also support full 250-MB/s packet throughput in each direction simultaneously. A cut-through architecture is implemented to reduce the latency associated with packets moving through the PCI Express fabric. As soon as the address or routing information is decoded within the header of a packet entering an ingress port, the packet is directed to the egress port for forwarding. Packet poisoning using the EDB framing signal is supported in circumstances where packet errors are detected after the transmission of the egress packet begins. The downstream ports may be configured to support PCI Hot Plug slot implementations. In this scenario, the system designer may decide to use the integrated PCI Hot Plug-compliant controller. This feature is available through the classic PCI configuration space under the PCI Express Capability Structure. When enabled, the downstream ports provide the PCI Hot Plug standard mechanism to apply and remove power to the slot or socket. Power-management features include Active State Power Management, PME mechanisms, the Beacon/Wake protocol, and all conventional PCI D-states. When ASPM is enabled, each link automatically saves power when idle using the L0s and L1 states. PME messages are supported along with the PME_Turn_Off/PME_TO_Ack protocol. When enabled, the upstream port supports Beacon transmission as well as theWAKEside band signal to wake the system as the result of a PCI Hot Plug event. Furthermore, the downstream ports may be configured to detect Beacon from downstream devices and forward this upstream. The switch also supports the translation and forwarding ofWAKEfrom a downstream device into Beacon on the upstream port for cabled implementations.