74AHC74PW-Q100 Series

Dual D-type flip-flop with set and reset; positive-edge trigger

Manufacturer: Freescale Semiconductor - NXP

Catalog

Dual D-type flip-flop with set and reset; positive-edge trigger

Part	Mounting Type	Trigger Type	Input Capacitance	Operating Temperature [Min]	Operating Temperature [Max]	Number of Bits per Element	Clock Frequency	Voltage - Supply [Max]	Voltage - Supply [Min]	Package / Case [x]	Package / Case [y]	Package / Case	Supplier Device Package	Number of Elements	Output Type	Max Propagation Delay @ V, Max CL	Current - Quiescent (Iq)	Function	Type	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Package / Case [custom]	Package / Case [custom]	Grade	Qualification
Freescale Semiconductor - NXP 74AHC74D,118	Surface Mount	Positive Edge	3 pF	-40 °C	125 °C	1	115 MHz	5.5 V	2 V	0.154 in	3.9 mm	14-SOIC	14-SO	2	Complementary	9.3 ns	2 µA	Reset Set(Preset)	D-Type	8 mA	8 mA
Freescale Semiconductor - NXP 74AHC74PW-Q100J	Surface Mount	Positive Edge	3 pF	-40 °C	125 °C	1	115 MHz	5.5 V	2 V			14-TSSOP	14-TSSOP	2	Complementary	9.3 ns	2 µA	Reset Set(Preset)	D-Type	8 mA	8 mA	0.173 "	4.4 mm	Automotive	AEC-Q100
Freescale Semiconductor - NXP 74AHC74D,112	Surface Mount	Positive Edge	3 pF	-40 °C	125 °C	1	115 MHz	5.5 V	2 V	0.154 in	3.9 mm	14-SOIC	14-SO	2	Complementary	9.3 ns	2 µA	Reset Set(Preset)	D-Type	8 mA	8 mA
Freescale Semiconductor - NXP 74AHC74PW,118	Surface Mount	Positive Edge	3 pF	-40 °C	125 °C	1	115 MHz	5.5 V	2 V			14-TSSOP	14-TSSOP	2	Complementary	9.3 ns	2 µA	Reset Set(Preset)	D-Type	8 mA	8 mA	0.173 "	4.4 mm

Catalog

Dual D-type flip-flop with set and reset; positive-edge trigger

Key Features

• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

Description

The 74AHC74-Q100; 74AHCT74-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.