66AK2H14DAAWA24

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Texas Instruments

HIGH PERFORMANCE MULTICORE DSP+ARM - 4X ARM A15 CORES, 8X C66X DSP CORES, 10GBE

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Search across all available documentation for this part.

DocumentsHardware Design Guide for KeyStone II Devices Security Accelerator (SA) for KeyStone Devices User's Guide (Rev. B)+67

66AK2H14DAAWA24

Active

Texas Instruments

HIGH PERFORMANCE MULTICORE DSP+ARM - 4X ARM A15 CORES, 8X C66X DSP CORES, 10GBE

Deep-Dive with AI

DocumentsHardware Design Guide for KeyStone II Devices Security Accelerator (SA) for KeyStone Devices User's Guide (Rev. B)+67

Specifications Pricing Series Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	66AK2H14DAAWA24

Clock Rate	1.2 GHz, 1.4 GHz
Interface	EBI/EMI, UART/USART, USB 3.0, Ethernet, I2C, SPI, Serial RapidIO, DMA
Mounting Type	Surface Mount
Non-Volatile Memory	384 kB
On-Chip RAM	12.75 MB
Operating Temperature [Max]	100 °C
Operating Temperature [Min]	-40 °C
Package / Case	FCBGA, 1517-BBGA
Supplier Device Package	1517-FCBGA (40x40)
Type	DSP+ARM®
Voltage - Core	Variable
Voltage - I/O	1.5 V, 1.35 V, 3.3 V, 1 V, 1.8 V, 0.85 V

66AK2H14 Series

High performance multicore DSP+Arm - 4x Arm A15 cores, 8x C66x DSP cores, 10GbE

Part	Operating Temperature [Min]	Operating Temperature [Max]	Clock Rate	Voltage - I/O	Supplier Device Package	Mounting Type	On-Chip RAM	Voltage - Core	Non-Volatile Memory	Package / Case	Interface	Type
Texas Instruments 66AK2H14DAAWA24	-40 °C	100 °C	1.2 GHz 1.4 GHz	0.85 V 1 V 1.35 V 1.5 V 1.8 V 3.3 V	1517-FCBGA (40x40)	Surface Mount	12.75 MB	Variable	384 kB	1517-BBGA FCBGA	DMA EBI/EMI Ethernet I2C Serial RapidIO SPI UART/USART USB 3.0	DSP+ARM®

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tray	21	$ 1188.92
LCSC	Piece	1	$ 546.18
		21	$ 518.73
Texas Instruments	JEDEC TRAY (5+1)	1	$ 1075.19
		100	$ 973.24
		250	$ 945.43
		1000	$ 926.89

Description

General part information

66AK2H14 Series

The 66AK2Hxx platform combines the quad ARM Cortex-A15 processor with up to eight TMS320C66x high-performance DSPs using the KeyStone II architecture. The 66AK2H14/12/06 device provides up to 5.6 GHz of ARM and 9.6 GHz of DSP processing coupled with security, packet processing, and Ethernet switching at lower power than multichip solutions. The 66AK2H14/12/06 device is optimal for embedded infrastructure applications like cloud computing, media processing, high-performance computing, transcoding, security, gaming, analytics, and virtual desktop.

The C66x core combines fixed-point and floating-point computational capability in the processor without sacrificing speed, size, or power consumption. The raw computational performance is 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz operating frequency). The C66x is also 100% backward compatible with software for C64x+ devices. The C66x core incorporates 90 new instructions targeted for floating point (FPi) and vector math oriented (VPi) processing.

The 66AK2H14/12/06 device has a complete set of development tools that includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows®debugger interface for visibility into source code execution.

Documents

Technical documentation and resources

66AK2H14DAAWA24

Deep-Dive with AI

66AK2H14DAAWA24

Deep-Dive with AI

Technical Specifications

66AK2H14 Series

Pricing

Description

66AK2H14 Series

Documents

Hardware Design Guide for KeyStone II Devices

Security Accelerator (SA) for KeyStone Devices User's Guide (Rev. B)

KeyStone™-II-based processors: 10G Ethernet as an optical interface

Introduction to HVDC Architecture and Solutions for Control and Protection (Rev. B)

Packet Accelerator (PA) for KeyStone Devices User's Guide (Rev. A)

The Case for 10G Ethernet in Embedded Processing

Multicore Shared Memory Controller (MSMC) User Guide for KeyStone II Devices

TI’s processors leading the way in embedded analytics

PCIe Use Cases for KeyStone Devices

KeyStone II Architecture Universal Serial Bus 3.0 (USB 3.0) (Rev. A)

Keystone II DDR3 Debug Guide

ARM Optimizing C/C++ Compiler v5.2 User's Guide (Rev. J)

Serial RapidIO (SRIO) for KeyStone Devices User's Guide (Rev. C)

ARM Bootloader User Guide for KeyStone II Devices

66AK2Hxx Multicore DSP+ARM KeyStone II SOC Errata (Revs 1.0, 1.1, 2.0, 3.0, 3.1) (Rev. F)

Using DSPLIB FFT Implementation for Real Input and Without Data Scaling

DDR3 Design Requirements for KeyStone Devices (Rev. D)

Power Management of KS2 Device (Rev. C)

SERDES Link Commissioning on KeyStone I and II Devices

Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices UG

Using Arm ROM Bootloader on Keystone II Devices

General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide

External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A)

Multicore Programming Guide (Rev. B)

Clocking Design Guide for KeyStone Devices

Video Infrastructure - Applications of the K2E, K2H platforms

Multicore SoCs stay a step ahead of SoC FPGAs

Multicore DSPs for High-Performance Video Coding

Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A)

Serializer/Deserializer (SerDes) for KeyStone II Devices User Guide (Rev. A)

C66x CPU and Instruction Set Reference Guide

KeyStone II DDR3 interface bring-up

Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B)

Keystone Multicore Device Family Schematic Checklist

Keystone Error Detection and Correction EDC ECC (Rev. A)

DDR3 Memory Controller for KeyStone II Devices User's Guide (Rev. C)

Industrial Imaging: Applications of the K2H and K2E platforms

64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A)

Designing professional audio mixers for every scenario

Network Coprocessor for KeyStone Devices User's Guide

Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H)

How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A)

10 Gigabit Ethernet Switch Subsystem User Guide for KeyStone II Devices

Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A)

C66x CorePac User's Guide (Rev. C)

66AK2Hxx Multicore DSP+ARM® KeyStone II System-on-Chip (SoC) datasheet (Rev. G)

HyperLink for KeyStone Devices User's Guide (Rev. C)

Keystone II DDR3 Initialization

TI DSP Benchmarking

PCI Express (PCIe) for KeyStone Devices User's Guide (Rev. D)

Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C)

Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A)

Gigabit Ethernet Switch Subsystem for KeyStone Devices User's Guide (Rev. D)

PCI Express (PCIe) Resource Wiki for Keystone Devices (Rev. A)

Thermal Design Guide for DSP and Arm Application Processors (Rev. B)

Optimizing Loops on the C66x DSP

Introduction to TMS320C6000 DSP Optimization

Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide

66AK2Hx KeyStone Multicore DSP+ARM System-on-chips (Rev. A)

Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I)

Debug and Trace for KeyStone II Devices User's Guide

ARM CorePac User Guide for KeyStone II Devices

C66x DSP Cache User's Guide

Software and Hardware Design Challenges Due to Dynamic Raw NAND Market

ARM Assembly Language Tools v5.2 User's Guide (Rev. M)

Implementing an FTP Server on TI 66AK2H Device With RTOS

Throughput Performance Guide for KeyStone II Devices (Rev. B)

DSP Bootloader for KeyStone Architecture User's Guide (Rev. C)

Datasheet

66AK2H14 Series