66AK2H06DAAW2

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Texas Instruments

HIGH PERFORMANCE MULTICORE DSP+ARM - 2X ARM A15 CORES, 4X C66X DSP CORES

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66AK2H06DAAW2

Active

Texas Instruments

HIGH PERFORMANCE MULTICORE DSP+ARM - 2X ARM A15 CORES, 4X C66X DSP CORES

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DocumentsDatasheet Multicore SoCs stay a step ahead of SoC FPGAs +64

Specifications Pricing Series Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	66AK2H06DAAW2

Clock Rate	1.2 GHz
Interface	EBI/EMI, UART/USART, USB 3.0, Ethernet, I2C, SPI, Serial RapidIO, DMA
Mounting Type	Surface Mount
Non-Volatile Memory	384 kB
On-Chip RAM	8.375 MB
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	0 °C
Package / Case	FCBGA, 1517-BBGA
Supplier Device Package	1517-FCBGA (40x40)
Type	DSP+ARM®
Voltage - Core	Variable
Voltage - I/O	1.5 V, 1.35 V, 3.3 V, 1 V, 1.8 V, 0.85 V

66AK2H06 Series

High performance multicore DSP+Arm - 2x Arm A15 cores, 4x C66x DSP cores

Part	Supplier Device Package	Type	On-Chip RAM	Clock Rate	Mounting Type	Voltage - Core	Interface	Operating Temperature [Max]	Operating Temperature [Min]	Package / Case	Voltage - I/O	Non-Volatile Memory
Texas Instruments 66AK2H06DAAW2	1517-FCBGA (40x40)	DSP+ARM®	8.375 MB	1.2 GHz	Surface Mount	Variable	DMA EBI/EMI Ethernet I2C Serial RapidIO SPI UART/USART USB 3.0	85 °C	0 °C	1517-BBGA FCBGA	0.85 V 1 V 1.35 V 1.5 V 1.8 V 3.3 V	384 kB
Texas Instruments 66AK2H06DAAWA24	1517-FCBGA (40x40)	DSP+ARM®	8.375 MB	1.2 GHz 1.4 GHz	Surface Mount	Variable	DMA EBI/EMI Ethernet I2C Serial RapidIO SPI UART/USART USB 3.0	100 °C	-40 °C	1517-BBGA FCBGA	0.85 V 1 V 1.35 V 1.5 V 1.8 V 3.3 V	384 kB
Texas Instruments 66AK2H06DAAW24	1517-FCBGA (40x40)	DSP+ARM®	8.375 MB	1.2 GHz 1.4 GHz	Surface Mount	Variable	DMA EBI/EMI Ethernet I2C Serial RapidIO SPI UART/USART USB 3.0	85 °C	0 °C	1517-BBGA FCBGA	0.85 V 1 V 1.35 V 1.5 V 1.8 V 3.3 V	384 kB
Texas Instruments 66AK2H06BAAW2	1517-FCBGA (40x40)	DSP+ARM®	8.375 MB	1.2 GHz	Surface Mount	Variable	DMA EBI/EMI Ethernet I2C Serial RapidIO SPI UART/USART USB 3.0	85 °C	0 °C	1517-BBGA FCBGA	0.85 V 1 V 1.35 V 1.5 V 1.8 V 3.3 V	384 kB
Texas Instruments 66AK2H06AAAW2	1517-FCBGA (40x40)	DSP+ARM®	8.375 MB	1.2 GHz	Surface Mount	Variable	DMA EBI/EMI Ethernet I2C Serial RapidIO SPI UART/USART USB 3.0	85 °C	0 °C	1517-BBGA FCBGA	0.85 V 1 V 1.35 V 1.5 V 1.8 V 3.3 V	384 kB
Texas Instruments 66AK2H06DXAAW2

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tray	21	$ 484.37
Texas Instruments	JEDEC TRAY (5+1)	1	$ 431.25
		100	$ 390.35
		250	$ 379.20
		1000	$ 371.77

Description

General part information

66AK2H06 Series

The 66AK2Hxx platform combines the quad ARM Cortex-A15 processor with up to eight TMS320C66x high-performance DSPs using the KeyStone II architecture. The 66AK2H14/12/06 device provides up to 5.6 GHz of ARM and 9.6 GHz of DSP processing coupled with security, packet processing, and Ethernet switching at lower power than multichip solutions. The 66AK2H14/12/06 device is optimal for embedded infrastructure applications like cloud computing, media processing, high-performance computing, transcoding, security, gaming, analytics, and virtual desktop.

The C66x core combines fixed-point and floating-point computational capability in the processor without sacrificing speed, size, or power consumption. The raw computational performance is 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz operating frequency). The C66x is also 100% backward compatible with software for C64x+ devices. The C66x core incorporates 90 new instructions targeted for floating point (FPi) and vector math oriented (VPi) processing.

The 66AK2H14/12/06 device has a complete set of development tools that includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows®debugger interface for visibility into source code execution.

Documents

Technical documentation and resources

66AK2H06DAAW2

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66AK2H06DAAW2

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Technical Specifications

66AK2H06 Series

Pricing

Description

66AK2H06 Series

Documents

Datasheet

Multicore SoCs stay a step ahead of SoC FPGAs

Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B)

ARM Assembly Language Tools v5.2 User's Guide (Rev. M)

Hardware Design Guide for KeyStone II Devices

Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C)

Introduction to HVDC Architecture and Solutions for Control and Protection (Rev. B)

PCI Express (PCIe) for KeyStone Devices User's Guide (Rev. D)

DSP Bootloader for KeyStone Architecture User's Guide (Rev. C)

Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices UG

Keystone Multicore Device Family Schematic Checklist

ARM Bootloader User Guide for KeyStone II Devices

KeyStone II Architecture Universal Serial Bus 3.0 (USB 3.0) (Rev. A)

TI DSP Benchmarking

Software and Hardware Design Challenges Due to Dynamic Raw NAND Market

SERDES Link Commissioning on KeyStone I and II Devices

ARM CorePac User Guide for KeyStone II Devices

Using Arm ROM Bootloader on Keystone II Devices

Security Accelerator (SA) for KeyStone Devices User's Guide (Rev. B)

Implementing an FTP Server on TI 66AK2H Device With RTOS

Power Management of KS2 Device (Rev. C)

Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A)

66AK2Hx KeyStone Multicore DSP+ARM System-on-chips (Rev. A)

Keystone Error Detection and Correction EDC ECC (Rev. A)

External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A)

Thermal Design Guide for DSP and Arm Application Processors (Rev. B)

ARM Optimizing C/C++ Compiler v5.2 User's Guide (Rev. J)

Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide

Multicore Shared Memory Controller (MSMC) User Guide for KeyStone II Devices

PCIe Use Cases for KeyStone Devices

Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A)

Keystone II DDR3 Initialization

Multicore Programming Guide (Rev. B)

Multicore DSPs for High-Performance Video Coding

C66x DSP Cache User's Guide

Clocking Design Guide for KeyStone Devices

Power Consumption Summary for 66AK2Hx System-on-Chip (SoC) Device Family

Serial RapidIO (SRIO) for KeyStone Devices User's Guide (Rev. C)

Debug and Trace for KeyStone II Devices User's Guide

C66x CorePac User's Guide (Rev. C)

Keystone II DDR3 Debug Guide

Throughput Performance Guide for KeyStone II Devices (Rev. B)

Network Coprocessor for KeyStone Devices User's Guide

Video Infrastructure - Applications of the K2E, K2H platforms

Using DSPLIB FFT Implementation for Real Input and Without Data Scaling

DDR3 Design Requirements for KeyStone Devices (Rev. D)

Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A)

TI’s processors leading the way in embedded analytics

Industrial Imaging: Applications of the K2H and K2E platforms

Packet Accelerator (PA) for KeyStone Devices User's Guide (Rev. A)

66AK2Hxx Multicore DSP+ARM KeyStone II SOC Errata (Revs 1.0, 1.1, 2.0, 3.0, 3.1) (Rev. F)

Optimizing Loops on the C66x DSP

66AK2Hxx Multicore DSP+ARM® KeyStone II System-on-Chip (SoC) datasheet (Rev. G)

How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A)

General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide

HyperLink for KeyStone Devices User's Guide (Rev. C)

Introduction to TMS320C6000 DSP Optimization

C66x CPU and Instruction Set Reference Guide

64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A)

KeyStone™-II-based processors: 10G Ethernet as an optical interface

KeyStone II DDR3 interface bring-up

DDR3 Memory Controller for KeyStone II Devices User's Guide (Rev. C)

Serializer/Deserializer (SerDes) for KeyStone II Devices User Guide (Rev. A)

Gigabit Ethernet Switch Subsystem for KeyStone Devices User's Guide (Rev. D)

Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I)

Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H)

66AK2H06 Series