66AK2L06XCMS2

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Texas Instruments

MULTICORE DSP+ARM KEYSTONE II SYSTEM-ON-CHIP (SOC)

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Search across all available documentation for this part.

DocumentsARM CorePac User Guide for KeyStone II Devices Semaphore2 Hardware Module for KeyStone Devices User's Guide (Rev. A)+64

66AK2L06XCMS2

Active

Texas Instruments

MULTICORE DSP+ARM KEYSTONE II SYSTEM-ON-CHIP (SOC)

Deep-Dive with AI

DocumentsARM CorePac User Guide for KeyStone II Devices Semaphore2 Hardware Module for KeyStone Devices User's Guide (Rev. A)+64

Specifications Pricing Series Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	66AK2L06XCMS2

Clock Rate	1.2 GHz
Interface	DMA, UART/USART, Ethernet, USB 3.0, USIM, SPI, I2C, PCIe, EBI/EMI
Mounting Type	Surface Mount
Non-Volatile Memory	384 kB
On-Chip RAM	5.384 MB
Operating Temperature [Max]	100 °C
Operating Temperature [Min]	0 °C
Package / Case	900-BFBGA, FCBGA
Supplier Device Package	900-FCBGA (25x25)
Type	DSP+ARM®
Voltage - Core	Variable
Voltage - I/O	3.3 V, 1 V, 1.8 V, 0.85 V

66AK2L06 Series

Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

Part	Supplier Device Package	Type	Mounting Type	Non-Volatile Memory	On-Chip RAM	Clock Rate	Package / Case	Interface	Operating Temperature [Max]	Operating Temperature [Min]	Voltage - I/O	Voltage - Core
Texas Instruments 66AK2L06XCMS2	900-FCBGA (25x25)	DSP+ARM®	Surface Mount	384 kB	5.384 MB	1.2 GHz	900-BFBGA FCBGA	DMA EBI/EMI Ethernet I2C PCIe SPI UART/USART USB 3.0 USIM	100 °C	0 °C	0.85 V 1 V 1.8 V 3.3 V	Variable
Texas Instruments 66AK2L06XCMS	900-FCBGA (25x25)	DSP+ARM®	Surface Mount	384 kB	5.384 MB		900-BFBGA FCBGA	DMA EBI/EMI Ethernet I2C PCIe SPI UART/USART USB 3.0 USIM	100 °C	0 °C	0.85 V 1 V 1.8 V 3.3 V	Variable
Texas Instruments 66AK2L06XCMSA2	900-FCBGA (25x25)	DSP+ARM®	Surface Mount	384 kB	5.384 MB	1.2 GHz	900-BFBGA FCBGA	DMA EBI/EMI Ethernet I2C PCIe SPI UART/USART USB 3.0 USIM	100 °C	-40 °C	0.85 V 1 V 1.8 V 3.3 V	Variable
Texas Instruments 66AK2L06XCMSA	900-FCBGA (25x25)	DSP+ARM®	Surface Mount	384 kB	5.384 MB		900-BFBGA FCBGA	DMA EBI/EMI Ethernet I2C PCIe SPI UART/USART USB 3.0 USIM	100 °C	-40 °C	0.85 V 1 V 1.8 V 3.3 V	Variable

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tray	44	$ 584.72
Texas Instruments	JEDEC TRAY (5+1)	1	$ 524.65
		100	$ 474.90
		250	$ 461.33
		1000	$ 452.29

Description

General part information

66AK2L06 Series

The 66AK2L06 KeyStone SoC is a member of the C66x family based on TI's new KeyStone II Multicore SoC Architecture and is a low-power solution with integrated JESD204B lanes that meets the more stringent power, size, and cost requirements of applications requiring connectivity with ADC and DAC based applications. The device’s ARM and DSP cores deliver exceptional processing power on platforms requiring high signal and control processing.

TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (ARM CorePac, C66x CorePacs, IP network, Digital Front End, and FFT processing) and uses a queue-based communication system that allows the SoC resources to operate efficiently and seamlessly. This unique SoC architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to dedicated coprocessors and high-speed IO, to each operate at maximum efficiency with no blocking or stalling.

The addition of the ARM CorePac in the 66AK2L06 device enables the ability for complex control code processing on-chip. Operations such as housekeeping and management processing can be performed with the Cortex-A15 processor.

Documents

Technical documentation and resources

66AK2L06XCMS2

Deep-Dive with AI

66AK2L06XCMS2

Deep-Dive with AI

Technical Specifications

66AK2L06 Series

Pricing

Description

66AK2L06 Series

Documents

ARM CorePac User Guide for KeyStone II Devices

Semaphore2 Hardware Module for KeyStone Devices User's Guide (Rev. A)

Are 66AK2L06 SoCs an answer to miniaturization of test and measurement equipment?

Packet Accelerator 2 (PA2) for K2E and K2L Devices User's Guide

Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide

66AK2L06 JESD Attach to ADC12J4000 / DAC38J84 Design Guide (Rev. A)

Keystone Error Detection and Correction EDC ECC (Rev. A)

Clocking Design Guide for KeyStone Devices

Power Management of KS2 Device (Rev. C)

Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H)

Digital Front End (DFE) for Keystone II Devices User's Guide (Rev. A)

66AK2L06 JESD Attach to ADC12J4000/DAC38J84 Getting Started Guide (Rev. B)

C66x DSP Cache User's Guide

Gigabit Ethernet (GbE) Switch SS for K2E & K2L Devices User's Guide (Rev. A)

TPS544Bxx/TPS544Cxx Powering TCI6630K2L in Smart Reflex Class 0 TC Mode

66AK2L06 SoC Product Bulletin

External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A)

Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A)

DSP Bootloader for KeyStone Architecture User's Guide (Rev. C)

Optimizing synthetic aperture radar design with TI's integrated 66AK2L06 SoC

C66x CorePac User's Guide (Rev. C)

Keystone EDMA FAQ

Thermal Design Guide for DSP and Arm Application Processors (Rev. B)

C66x CPU and Instruction Set Reference Guide

DDR3 Design Requirements for KeyStone Devices (Rev. D)

Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B)

Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C)

SERDES Link Commissioning on KeyStone I and II Devices

Accelerating the Fast Fourier Transform (FFT/iFFT) by 10x and more

How to complete your RF sampling solution

Throughput Performance Guide for KeyStone II Devices (Rev. B)

Optimizing Loops on the C66x DSP

Optimizing Modern Radar Systems using Low- Latency, High-Performance FFT Coproce

System solution for avionics & defense

66AK2Lxx Multicore DSP+ARM KeyStone II SOC (Silicon Revision 1.0)

Security Accelerator 2 (SA2) for K2E and K2L Devices User's Guide

PCIe Use Cases for KeyStone Devices

Keystone II DDR3 Debug Guide

Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A)

Keystone II DDR3 Initialization

Fast Fourier Transform Coprocessor (FFTC) for KeyStone II Devices User's Guide (Rev. A)

Wireless infrastructure - Now simpler and more accessible!

Using Arm ROM Bootloader on Keystone II Devices

Introduction to TMS320C6000 DSP Optimization

Serializer/Deserializer (SerDes) for KeyStone II Devices User Guide (Rev. A)

TI DSP Benchmarking

Wideband Receiver With 66AK2L06 JESD204B Attach to ADC32RF80 Reference Design

General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide

Multicore Programming Guide (Rev. B)

Network Coprocessor (NETCP) for K2E and K2L Devices User's Guide

Software and Hardware Design Challenges Due to Dynamic Raw NAND Market

Hardware Design Guide for KeyStone II Devices

Ready to make the jump to JESD204B? White Paper (Rev. B)

Multicore Shared Memory Controller (MSMC) User Guide for KeyStone II Devices

Multicore SoCs stay a step ahead of SoC FPGAs

Summertime showdown: DSPs vs FPGAs

Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I)

DDR3 Memory Controller for KeyStone II Devices User's Guide (Rev. C)

Optimizing your test and measurement solution by leveraging the most integrated

64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A)

IQN2 for KeyStone II Devices User's Guide (Rev. A)

Debug and Trace for KeyStone II Devices User's Guide

Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A)

KeyStone II Architecture Universal Serial Bus 3.0 (USB 3.0) (Rev. A)

Datasheet

66AK2L06 Product Bulletin

66AK2L06 Series