
74AUP2G125RA3-7
ActiveBUS DRIVER, AUP/ULP/V SERIES, 2-FUNC, 1-BIT, TRUE OUTPUT, CMOS, PDSO8, 1.20 X 1 MM, 0.35 MM HEIGHT, 0.30 MM PITCH, GREEN, DFN-8
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74AUP2G125RA3-7
ActiveBUS DRIVER, AUP/ULP/V SERIES, 2-FUNC, 1-BIT, TRUE OUTPUT, CMOS, PDSO8, 1.20 X 1 MM, 0.35 MM HEIGHT, 0.30 MM PITCH, GREEN, DFN-8
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Technical Specifications
Parameters and characteristics for this part
| Specification | 74AUP2G125RA3-7 |
|---|---|
| Current - Output High, Low [custom] | 4 mA |
| Current - Output High, Low [custom] | 4 mA |
| Logic Type | Buffer, Non-Inverting |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 1 |
| Number of Elements | 2 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | 3-State |
| Package / Case | 8-XFDFN |
| Supplier Device Package | X2-DFN1210-8 |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 0.8 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 0.68 | |
| 10 | $ 0.42 | |||
| 25 | $ 0.35 | |||
| 100 | $ 0.27 | |||
| 250 | $ 0.23 | |||
| 500 | $ 0.21 | |||
| 1000 | $ 0.19 | |||
| 2500 | $ 0.17 | |||
| Digi-Reel® | 1 | $ 0.68 | ||
| 10 | $ 0.42 | |||
| 25 | $ 0.35 | |||
| 100 | $ 0.27 | |||
| 250 | $ 0.23 | |||
| 500 | $ 0.21 | |||
| 1000 | $ 0.19 | |||
| 2500 | $ 0.17 | |||
| Tape & Reel (TR) | 5000 | $ 0.15 | ||
| 10000 | $ 0.14 | |||
| 15000 | $ 0.14 | |||
| 25000 | $ 0.13 | |||
| 35000 | $ 0.13 | |||
| 50000 | $ 0.12 | |||
Description
General part information
74AUP2G125 Series
The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP2G125 is a dual 3-State Buffer. Each buffer has an individual output enable pin while asserted HIGH will place the output in a high impedance state. The device is designed for operation over a power supply range of 0.8 V to 3.6 V. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output preventing damaging current backflow when the device is powered down.
Documents
Technical documentation and resources