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XIO2213AZAY - 167-LFBGA

XIO2213AZAY

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Texas Instruments

X1 PCI EXPRESS TO 1394B OHCI AND 3-PORT PHY

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XIO2213AZAY - 167-LFBGA

XIO2213AZAY

Active
Texas Instruments

X1 PCI EXPRESS TO 1394B OHCI AND 3-PORT PHY

Technical Specifications

Parameters and characteristics for this part

SpecificationXIO2213AZAY
ApplicationsPC's, PDA's
InterfacePCI
Mounting TypeSurface Mount
Package / Case167-LFBGA
Supplier Device Package167-NFBGA (12x12)
Voltage - Supply3.3 V, 1.95 V, 1.5 V

XIO2213B Series

x1 PCI Express to 1394b OHCI and 3-port PHY

PartPackage / CaseVoltage - SupplySupplier Device PackageApplicationsMounting TypeInterfaceFunctionSupplied ContentsTypeUtilized IC / Part
Texas Instruments
167-LFBGA
1.5 V
1.95 V
3.3 V
167-NFBGA (12x12)
PC's
PDA's
Surface Mount
PCI
Texas Instruments
167-LFBGA
1.5 V
1.95 V
3.3 V
167-NFBGA (12x12)
Surface Mount
Texas Instruments
PCI Express to IEEE 1394b OHCI
Board(s)
Interface
XIO2213B
Texas Instruments
167-LFBGA
1.5 V
1.95 V
3.3 V
167-NFBGA (12x12)
PC's
PDA's
Surface Mount
PCI
Texas Instruments
PCI Express to IEEE 1394b OHCI
Board(s)
Interface
XIO2213A

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTray 160$ 18.57
Texas InstrumentsJEDEC TRAY (5+1) 1$ 23.09
100$ 20.17
250$ 15.55
1000$ 13.91

Description

General part information

XIO2213B Series

The Texas Instruments XIO2213A is a PCI Express to PCI translation bridge where the PCI bus interface is internally connected to a 1394b open host controller link-layer controller with a three-port 1394b PHY. The PCI-Express to PCI translation bridge is fully compatible with thePCI Express to PCI/PCI-X Bridge Specification, Revision 1.0. Also, the bridge supports the standard PCI-to-PCI bridge programming model. The 1394b OHCI controller function is fully compatible with IEEE Standard1394b and the latest 1394 Open Host Controller Interface (OHCI)Specification.

The XIO2213A simultaneously supports up to four posted write transactions, four non-posted transactions, and four completion transactions pending in each direction at any time. Each posted write data queue and completion data queue can store up to 8K bytes of data. The non-posted data queues can store up to 128 bytes of data.

The PCI Express interface supports a x1 link operating at full 250 MB/s packet throughput in each direction simultaneously. Also, the bridge supports the advanced error reporting capability including ECRC as defined in thePCI Express Base Specification,Revision 1.1. Supplemental firmware or software is required to fully utilize both of these features.