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UC3525AQTRG3 - 20-PLCC

UC3525AQTRG3

Obsolete
Texas Instruments

IC REG CTRLR MULT TOP 20PLCC

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UC3525AQTRG3 - 20-PLCC

UC3525AQTRG3

Obsolete
Texas Instruments

IC REG CTRLR MULT TOP 20PLCC

Deep-Dive with AI

DocumentsDatasheet

Technical Specifications

Parameters and characteristics for this part

SpecificationUC3525AQTRG3
Clock SyncTrue
Control FeaturesFrequency Control, Enable, Soft Start
Duty Cycle (Max)49 %
Frequency - Switching [Max]400 kHz
Frequency - Switching [Min]100 Hz
FunctionStep-Up, Step-Up/Step-Down, Step-Down
Mounting TypeSurface Mount
Number of Outputs2
Operating Temperature [Max]70 °C
Operating Temperature [Min]0 °C
Output ConfigurationPositive
Output Phases1
Output TypeTransistor Driver
Package / Case20-LCC (J-Lead)
Supplier Device Package20-PLCC (9x9)
Synchronous RectifierTrue
TopologyForward Converter, Flyback, Push-Pull, Half-Bridge, Full-Bridge, Boost, Buck
Voltage - Supply (Vcc/Vdd) [Max]35 V
Voltage - Supply (Vcc/Vdd) [Min]8 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

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Description

General part information

UC3525A Series

The UC1525B/1527B series of pulse width modulator integrated circuits are designed to offer improved performance and lowered external parts count when used in designing all types of switching power supplies. The on-chip +5.1V buried zener reference is trimmed to ±0.75% and the input common-mode range of the error amplifier includes the reference voltage, eliminating external resistors. A sync input to the oscillator allows multiple units to be slaved or a single unit to be synchronized to an external system clock. A single resistor between the CT and the discharge terminals provide a wide range of dead time adjustment. These devices also feature built-in soft-start circuitry with only an external timing capacitor required. A shutdown terminal controls both the soft-start circuitry and the output stages, providing instantaneous turn off through the PWM latch with pulsed shutdown, as well as soft-start recycle with longer shutdown commands. These functions are also controlled by an undervoltage lockout which keeps the outputs off and the soft-start capacitor discharged for subnormal input voltages. This lockout circuitry includes approximately 500mV of hysteresis for jitter-free operation. Another feature of these PWM circuits is a latch following the comparator. Once a PWM pulse has been terminated for any reason, the outputs will remain off for the duration of the period. The latch is reset with each clock pulse. The output stages are totem-pole designs capable of sourcing or sinking in excess of 200mA. The UC1525B output stage features NOR logic, giving a LOW output for an OFF state. The UC1527B utilizes OR logic which results in a HIGH output level when OFF.

The UC1525B/1527B series of pulse width modulator integrated circuits are designed to offer improved performance and lowered external parts count when used in designing all types of switching power supplies. The on-chip +5.1V buried zener reference is trimmed to ±0.75% and the input common-mode range of the error amplifier includes the reference voltage, eliminating external resistors. A sync input to the oscillator allows multiple units to be slaved or a single unit to be synchronized to an external system clock. A single resistor between the CT and the discharge terminals provide a wide range of dead time adjustment. These devices also feature built-in soft-start circuitry with only an external timing capacitor required. A shutdown terminal controls both the soft-start circuitry and the output stages, providing instantaneous turn off through the PWM latch with pulsed shutdown, as well as soft-start recycle with longer shutdown commands. These functions are also controlled by an undervoltage lockout which keeps the outputs off and the soft-start capacitor discharged for subnormal input voltages. This lockout circuitry includes approximately 500mV of hysteresis for jitter-free operation. Another feature of these PWM circuits is a latch following the comparator. Once a PWM pulse has been terminated for any reason, the outputs will remain off for the duration of the period. The latch is reset with each clock pulse. The output stages are totem-pole designs capable of sourcing or sinking in excess of 200mA. The UC1525B output stage features NOR logic, giving a LOW output for an OFF state. The UC1527B utilizes OR logic which results in a HIGH output level when OFF.

Documents

Technical documentation and resources