SN54LS592J
Active8-BIT BINARY COUNTERS WITH INPUT REGISTERS
Deep-Dive with AI
Search across all available documentation for this part.
SN54LS592J
Active8-BIT BINARY COUNTERS WITH INPUT REGISTERS
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | SN54LS592J |
|---|---|
| Count Rate | 35 MHz |
| Direction | Up |
| Logic Type | Binary Counter |
| Mounting Type | Through Hole |
| Number of Bits per Element | 8 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Package / Case | 7.62 mm, 0.3 in |
| Package / Case | 16-CDIP |
| Reset | Asynchronous |
| Supplier Device Package | 16-CDIP |
| Trigger Type | Positive Edge |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 4.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Texas Instruments | TUBE | 1 | $ 30.69 | |
| 100 | $ 27.28 | |||
| 250 | $ 22.42 | |||
| 1000 | $ 20.06 | |||
Description
General part information
5962-8762101 Series
The 'LS592 comes in a 16-pin package and consists of a parallel input, 8-bit storage register feeding an 8-bit binary counter. Both the register and the counter have individual positive-edge-triggered clocks. In addition, the counter has direct load and clear functions. A low-going RCO\ pulse will be obtained when the counter reaches the hex word FF. Expansion is easily accomplished for two stages by connecting RCO\ of the first stage to CCKEN\ of the second stage. Cascading for larger count chains can be accomplished by connecting RCO\ of each stage to CCK of the following stage.
The 'LS593 comes in a 20-pin package and has all the features of the 'LS592 plus 3-state I/O, which provides parallel counter outputs. The tables below show the operation of the enable (CCKEN, CCKEN\) inputs. A register clock enable (RCKEN\) is also provided.
The 'LS592 comes in a 16-pin package and consists of a parallel input, 8-bit storage register feeding an 8-bit binary counter. Both the register and the counter have individual positive-edge-triggered clocks. In addition, the counter has direct load and clear functions. A low-going RCO\ pulse will be obtained when the counter reaches the hex word FF. Expansion is easily accomplished for two stages by connecting RCO\ of the first stage to CCKEN\ of the second stage. Cascading for larger count chains can be accomplished by connecting RCO\ of each stage to CCK of the following stage.
Documents
Technical documentation and resources