UCD9240RGCT
ActiveDC/DC CNTRLR SINGLE-OUT STEP DOWN 2000KHZ 64-PIN VQFN EP T/R
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UCD9240RGCT
ActiveDC/DC CNTRLR SINGLE-OUT STEP DOWN 2000KHZ 64-PIN VQFN EP T/R
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | UCD9240RGCT |
|---|---|
| Applications | Special Purpose |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 110 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 64-VFQFN Exposed Pad |
| Supplier Device Package | 64-VQFN (9x9) |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 11.91 | |
| Digi-Reel® | 1 | $ 11.91 | ||
| Tape & Reel (TR) | 250 | $ 8.79 | ||
| 500 | $ 8.22 | |||
| 1250 | $ 7.54 | |||
| Texas Instruments | SMALL T&R | 1 | $ 10.95 | |
| 100 | $ 9.57 | |||
| 250 | $ 7.38 | |||
| 1000 | $ 6.60 | |||
Description
General part information
UCD9240 Series
The UCD9240 is a multi-rail, multi-phase synchronous buck digital PWM controller designed for non-isolated DC/DC power applications. This device integrates dedicated circuitry for DC/DC loop management with flash memory and a serial interface to support configurability, monitoring and management.
The UCD9240 was designed to provide a wide variety of desirable features for non-isolated DC/DC converter applications while minimizing the total system component count by reducing external circuits. The solution integrates multi-loop management with sequencing, margining, tracking and intelligent phase management to optimize for total system efficiency. Additionally, loop compensation and calibration are supported without the need to add external components.
To facilitate configuring the device, the Texas Instruments Fusion Digital Power™ Designer is provided. This PC based Graphical User Interface offers an intuitive interface to the device. This tool allows the design engineer to configure the system operating parameters for the application, store the configuration to on-chip non-volatile memory and observe both frequency domain and time domain simulations for each of the power stage outputs.
Documents
Technical documentation and resources