Zenode.ai Logo
Beta
K
180M-51LF - 180-51 - Block Diagram

180M-51LF

Obsolete
Renesas Electronics Corporation

IC SS CLOCK GENERATOR 8SOIC

Deep-Dive with AI

Search across all available documentation for this part.

180M-51LF - 180-51 - Block Diagram

180M-51LF

Obsolete
Renesas Electronics Corporation

IC SS CLOCK GENERATOR 8SOIC

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

Specification180M-51LF
Differential - Input:OutputFalse
Divider/MultiplierFalse
Frequency - Max [Max]28 MHz
InputCrystal, Clock
Mounting TypeSurface Mount
Number of Circuits1
Operating Temperature [Max]70 °C
Operating Temperature [Min]0 °C
OutputCMOS
Package / Case8-SOIC
Package / Case [x]0.154 in
Package / Case [y]3.9 mm
PLLTrue
Ratio - Input:Output [custom]1:1
Supplier Device Package8-SOIC
TypeSpread Spectrum Clock Generator
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]3.135 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$

Description

General part information

180-51 Series

The 180-53 generates a low EMI output clock from a clock or crystal input. The device uses IDT's proprietary mix of analog and digital Phase-Locked Loop (PLL) technology to spread the frequency spectrum of the output, thereby reducing the frequency amplitude peaks by several dB. The 180-53 offers center spread selection of +/-0.625% and +/-1.875%. Refer to the MK1714-01/02 for the widest selection of input frequencies and multipliers. IDT offers a complete line of EMI reducing clock generators. Consult us when you need to remove crystals and oscillators from your board.

Documents

Technical documentation and resources