
309RILF
ObsoleteSERIAL PROGRAMMABLE TRIPLE PLL SS VERSACLOCK SYNTH
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309RILF
ObsoleteSERIAL PROGRAMMABLE TRIPLE PLL SS VERSACLOCK SYNTH
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | 309RILF |
|---|---|
| Differential - Input:Output | False |
| Divider/Multiplier | No |
| Divider/Multiplier | Yes |
| Frequency - Max [Max] | 200 MHz |
| Input | Crystal, Clock |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output | LVCMOS |
| Package / Case | 20-SSOP |
| Package / Case [custom] | 0.154 in |
| Package / Case [custom] | 3.9 mm |
| PLL | Yes with Bypass |
| Ratio - Input:Output | 1:9 |
| Supplier Device Package | 20-QSOP |
| Type | Clock/Frequency Synthesizer |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tube | 150 | $ 4.60 | |
Description
General part information
309R Series
The 309 is a versatile serially-programmable, triple PLL with spread spectrum clock source. The 309 can generate any frequency from 250kHz to 200 MHz, and up to 6 different output frequencies simultaneously. The outputs can be reprogrammed on-the-fly, and will lock to a new frequency in 10 ms or less. To reduce system EMI emissions, spread spectrum is available that supports modulation frequencies of 31 kHz and 120 kHz, as well as modulation amplitudes of +/-0.25% to +/-2.0%. Both center and down-spread options are available. The device includes a PDTS pin which tri-states the output clocks and powers down the entire chip. The 309 default for non-programmed start-up are buffered reference clock outputs on all clock output pins. IDT's VersaClockTM programming software allows the user to configure up to 9 outputs with target frequencies, spread spectrum capabilities or buffered reference clock outputs. The VersaClockTM software automatically configures the PLLs for optimal overall performance.
Documents
Technical documentation and resources