74LVC00AS14-13
ActiveIC: DIGITAL; NAND; CH: 4; IN: 2; CMOS; SMD; SO14; 1.65÷5.5VDC; LVC
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74LVC00AS14-13
ActiveIC: DIGITAL; NAND; CH: 4; IN: 2; CMOS; SMD; SO14; 1.65÷5.5VDC; LVC
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Technical Specifications
Parameters and characteristics for this part
| Specification | 74LVC00AS14-13 |
|---|---|
| Current - Output High, Low | 24 mA |
| Current - Quiescent (Max) [Max] | 10 µA |
| Input Logic Level - High [Max] | 2 V |
| Input Logic Level - High [Min] | 1.7 V |
| Input Logic Level - Low [Max] | 0.8 V |
| Input Logic Level - Low [Min] | 0.7 V |
| Logic Type | NAND Gate |
| Max Propagation Delay @ V, Max CL | 4.1 ns |
| Mounting Type | Surface Mount |
| Number of Circuits | 4 |
| Number of Inputs | 2 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 14-SOIC |
| Package / Case [x] | 0.154 in |
| Package / Case [y] | 3.9 mm |
| Supplier Device Package | 14-SO |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 1.65 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 0.37 | |
| 10 | $ 0.30 | |||
| 25 | $ 0.27 | |||
| 100 | $ 0.20 | |||
| 250 | $ 0.18 | |||
| 500 | $ 0.15 | |||
| 1000 | $ 0.11 | |||
| Digi-Reel® | 1 | $ 0.37 | ||
| 10 | $ 0.30 | |||
| 25 | $ 0.27 | |||
| 100 | $ 0.20 | |||
| 250 | $ 0.18 | |||
| 500 | $ 0.15 | |||
| 1000 | $ 0.11 | |||
| Tape & Reel (TR) | 2500 | $ 0.10 | ||
| 5000 | $ 0.10 | |||
| 12500 | $ 0.09 | |||
| 25000 | $ 0.08 | |||
| 62500 | $ 0.08 | |||
| 125000 | $ 0.08 | |||
| TME | N/A | 1 | $ 0.59 | |
| 5 | $ 0.42 | |||
| 10 | $ 0.34 | |||
| 100 | $ 0.18 | |||
Description
General part information
74LVC00A Series
The 74LVC00A provides four independent 2-input NAND gates. The device is designed for operation with a power supply range of 1.65V to 5.5V. The inputs are tolerant to 5.5V, allowing this device to be used in a mixed-voltage environment. The device is fully specified for partial power down applications using IOFF. The IOFFcircuitry disables the output, preventing damaging current backflow when the device is powered down.
Documents
Technical documentation and resources