72V83L20PAGI8

Obsolete

Renesas Electronics Corporation

IC FIFO ASYNC 2KX9X2 56TSSOP

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DocumentsDatasheet 72V81-72V85 Datasheet

72V83L20PAGI8

Obsolete

Renesas Electronics Corporation

IC FIFO ASYNC 2KX9X2 56TSSOP

Deep-Dive with AI

DocumentsDatasheet 72V81-72V85 Datasheet

Specifications Pricing Series Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	72V83L20PAGI8

Access Time	20 ns
Bus Directional	Uni-Directional
Current - Supply (Max) [Max]	120 mA
Data Rate	33.3 MHz
Expansion Type	Width, Depth
Function	Asynchronous
FWFT Support	False
Memory Size	36 K
Mounting Type	Surface Mount
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Package / Case	6.1 mm
Package / Case	0.24 in
Package / Case	56-TFSOP
Programmable Flags Support	False
Retransmit Capability	True
Supplier Device Package	56-TSSOP
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	3 V

72V83 Series

2K x 9 DualAsync FIFO, 3.3V

Part	Retransmit Capability	Voltage - Supply [Min]	Voltage - Supply [Max]	Bus Directional	Supplier Device Package	Access Time	Function	Data Rate	Package / Case	Package / Case	Package / Case	Current - Supply (Max) [Max]	Memory Size	Mounting Type	Operating Temperature [Max]	Operating Temperature [Min]	FWFT Support	Programmable Flags Support	Expansion Type
Renesas Electronics Corporation 72V83L20PAGI8		3 V	3.6 V	Uni-Directional	56-TSSOP	20 ns	Asynchronous	33.3 MHz	6.1 mm	0.24 in	56-TFSOP	120 mA	36 K	Surface Mount	85 °C	-40 °C			Depth Width

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Description

General part information

72V83 Series

The 72V83 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.