
308RLF
ObsoleteSERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER
Deep-Dive with AI
Search across all available documentation for this part.

308RLF
ObsoleteSERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | 308RLF |
|---|---|
| Differential - Input:Output | False |
| Divider/Multiplier | No |
| Divider/Multiplier | Yes |
| Frequency - Max [Max] | 200 MHz |
| Input | Crystal, Clock |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 70 °C |
| Operating Temperature [Min] | 0 °C |
| Output | LVCMOS |
| Package / Case | 20-SSOP |
| Package / Case [custom] | 0.154 in |
| Package / Case [custom] | 3.9 mm |
| PLL | Yes with Bypass |
| Ratio - Input:Output | 1:9 |
| Supplier Device Package | 20-QSOP |
| Type | Clock/Frequency Synthesizer |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tube | 100 | $ 6.54 | |
Description
General part information
308R Series
The 308 is a versatile serially programmable, quad PLL clock source. The 308 can generate any frequency from 250 kHz to 200 MHz, and up to 6 different output frequencies simultaneously. The outputs can be reprogrammed on the fly, and will lock to a new frequency in 10 ms or less. Smooth transitions (in which the clock duty cycle remains roughly 50%) are guaranteed if the output divider is not changed. The device includes a PDTS pin which tri-states the output clocks and powers down the entire chip. The 308 default for non-programmed start-up are buffered reference clock outputs on all clock output pins.
Documents
Technical documentation and resources