74AHC573PW,118
ActiveLATCH, 74AHC573, D TYPE TRANSPARENT, TRI STATE NON INVERTED, 8.8 NS, 8 MA, 20 PINS, TSSOP
Deep-Dive with AI
Search across all available documentation for this part.
74AHC573PW,118
ActiveLATCH, 74AHC573, D TYPE TRANSPARENT, TRI STATE NON INVERTED, 8.8 NS, 8 MA, 20 PINS, TSSOP
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | 74AHC573PW,118 |
|---|---|
| Circuit [custom] | 8 |
| Circuit [custom] | 8 |
| Current - Output High, Low [custom] | 8 mA |
| Current - Output High, Low [custom] | 8 mA |
| Delay Time - Propagation | 3.9 ns |
| Independent Circuits | 1 |
| Logic Type | D-Type Transparent Latch |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Tri-State |
| Package / Case | 20-TSSOP |
| Package / Case [x] | 0.173 in |
| Package / Case [y] | 4.4 mm |
| Supplier Device Package | 20-TSSOP |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
Description
General part information
74AHC573PW Series
The 74AHC573; 74AHCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH onOEcauses the outputs to assume a high-impedance OFF-state. Operation of theOEinput does not affect the state of the latches. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments.
Documents
Technical documentation and resources