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72T1875L6-7BB - 72T1875 - Block Diagram

72T1875L6-7BB

Obsolete
Renesas Electronics Corporation

16K X 18 / 32K X 9 TERASYNC FIFO, 2.5V

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72T1875L6-7BB - 72T1875 - Block Diagram

72T1875L6-7BB

Obsolete
Renesas Electronics Corporation

16K X 18 / 32K X 9 TERASYNC FIFO, 2.5V

Deep-Dive with AI

DocumentsDatasheet

Technical Specifications

Parameters and characteristics for this part

Specification72T1875L6-7BB
Access Time3.8 ns, 12 ns
Bus DirectionalUni-Directional
Current - Supply (Max) [Max]60 mA
Data Rate150 MHz, 66 MHz
Expansion TypeWidth, Depth
FunctionSynchronous, Asynchronous
FWFT SupportTrue
Memory Size288 K
Mounting TypeSurface Mount
Operating Temperature [Max]70 °C
Operating Temperature [Min]0 °C
Package / Case144-BGA
Programmable Flags SupportTrue
Retransmit CapabilityTrue
Supplier Device Package144-PBGA (13x13)
Voltage - Supply [Max]2.625 V
Voltage - Supply [Min]2.375 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

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Description

General part information

72T1875 Series

The 72T1875 is a 16K x 18 / 32K x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.

Documents

Technical documentation and resources