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72T18125L5BB - 72T18125 - Block Diagram

72T18125L5BB

Obsolete
Renesas Electronics Corporation

512K X 18 / 1M X 9 TERASYNC FIFO, 2.5V

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72T18125L5BB - 72T18125 - Block Diagram

72T18125L5BB

Obsolete
Renesas Electronics Corporation

512K X 18 / 1M X 9 TERASYNC FIFO, 2.5V

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

Specification72T18125L5BB
Access Time10 ns, 3.6 ns
Bus DirectionalUni-Directional
Current - Supply (Max) [Max]70 mA
Data Rate83 MHz, 200 MHz
Expansion TypeWidth, Depth
FunctionSynchronous, Asynchronous
FWFT SupportTrue
Mounting TypeSurface Mount
Operating Temperature [Max]70 °C
Operating Temperature [Min]0 °C
Package / Case240-BGA
Programmable Flags SupportTrue
Retransmit CapabilityTrue
Supplier Device Package240-PBGA (19x19)
Voltage - Supply [Max]2.625 V
Voltage - Supply [Min]2.375 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

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Description

General part information

72T18125 Series

The 72T18125 is a 512K x 18 / 1M x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.

Documents

Technical documentation and resources