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72T1865L5BBI - 72T1865 - Block Diagram

72T1865L5BBI

Obsolete
Renesas Electronics Corporation

8K X 18 / 16K X 9 TERASYNC FIFO, 2.5V

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72T1865L5BBI - 72T1865 - Block Diagram

72T1865L5BBI

Obsolete
Renesas Electronics Corporation

8K X 18 / 16K X 9 TERASYNC FIFO, 2.5V

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

Specification72T1865L5BBI
Access Time10 ns, 3.6 ns
Bus DirectionalUni-Directional
Current - Supply (Max) [Max]60 mA
Data Rate83 MHz, 200 MHz
Expansion TypeWidth, Depth
FunctionSynchronous, Asynchronous
FWFT SupportTrue
Memory Size144 K
Mounting TypeSurface Mount
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Package / Case144-BGA
Programmable Flags SupportTrue
Retransmit CapabilityTrue
Supplier Device Package144-PBGA (13x13)
Voltage - Supply [Max]2.625 V
Voltage - Supply [Min]2.375 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

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Description

General part information

72T1865 Series

The 72T1865 is a 8K x 18 / 16K x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.

Documents

Technical documentation and resources