
548G-05ILF
ObsoleteIC CLK/FREQ SYNTH 16TSSOP
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548G-05ILF
ObsoleteIC CLK/FREQ SYNTH 16TSSOP
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Technical Specifications
Parameters and characteristics for this part
| Specification | 548G-05ILF |
|---|---|
| Differential - Input:Output | False |
| Divider/Multiplier | No |
| Divider/Multiplier | Yes |
| Frequency - Max [Max] | 49.152 MHz |
| Input | Crystal, Clock |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output | CMOS |
| Package / Case | 16-TSSOP |
| Package / Case [x] | 0.173 in |
| Package / Case [y] | 4.4 mm |
| PLL | Yes with Bypass |
| Ratio - Input:Output [custom] | 1:2 |
| Supplier Device Package | 16-TSSOP |
| Type | Clock/Frequency Synthesizer, Fanout Buffer (Distribution) |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 3.15 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
Description
General part information
548-05 Series
The 548-05 is a low-cost, low-jitter, high-performance clock synthesizer designed to produce x16 and x24 clocks from T1 and E1 frequencies. Using Renesas’ patented analog/digital Phase-Locked Loop (PLL) techniques, the device uses a crystal or clock input to synthesize popular communications frequencies. Power down modes allow the chip to turn off completely, or the PLL and clock output to be turned off separately.
Documents
Technical documentation and resources