
71421LA55J
ObsoleteIC SRAM 16KBIT PARALLEL 52PLCC
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71421LA55J
ObsoleteIC SRAM 16KBIT PARALLEL 52PLCC
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Technical Specifications
Parameters and characteristics for this part
| Specification | 71421LA55J |
|---|---|
| Access Time | 55 ns |
| Memory Format | SRAM |
| Memory Interface | Parallel |
| Memory Organization | 2K x 8 |
| Memory Size | 16 Kbit |
| Memory Type | Volatile |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 70 °C |
| Operating Temperature [Min] | 0 °C |
| Package / Case | 52-LCC (J-Lead) |
| Supplier Device Package | 52-PLCC (19.13x19.13) |
| Technology | SRAM - Dual Port, Asynchronous |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 4.5 V |
| Write Cycle Time - Word, Page [custom] | 55 ns |
| Write Cycle Time - Word, Page [custom] | 55 ns |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
Description
General part information
71421LA Series
The 71421 is a high-speed 2K x 8 Dual-Port Static RAM with internal interrupt logic for interprocessor communications. It is designed to be used as a "SLAVE" Dual-Port RAM together with the 71321 "MASTER" Dual-Port in 16-bit-or-more word width systems which would result in full-speed, error free operation without the need for additional discrete logic. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode.
Documents
Technical documentation and resources