72V3641L15PFG8

Obsolete

Renesas Electronics Corporation

IC FIFO SYNC 1KX36 10NS 120TQFP

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DocumentsDatasheet 72V3631-72V3641 Datasheet

72V3641L15PFG8

Obsolete

Renesas Electronics Corporation

IC FIFO SYNC 1KX36 10NS 120TQFP

Deep-Dive with AI

DocumentsDatasheet 72V3631-72V3641 Datasheet

Specifications Pricing Series Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	72V3641L15PFG8

Access Time	10 ns
Bus Directional	Bi-Directional
Current - Supply (Max) [Max]	400 µA
Data Rate	66.7 MHz
Expansion Type	Width, Depth
Function	Synchronous
FWFT Support	True
Memory Size	36 K
Mounting Type	Surface Mount
Operating Temperature [Max]	70 °C
Operating Temperature [Min]	0 °C
Package / Case	120-LQFP
Programmable Flags Support	True
Retransmit Capability	True
Supplier Device Package	120-TQFP (14x14)
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	3 V

72V3641 Series

1K x 36 SyncFIFO, 3.3V

Part	Programmable Flags Support	Retransmit Capability	Voltage - Supply [Min]	Voltage - Supply [Max]	Operating Temperature [Max]	Operating Temperature [Min]	Access Time	Package / Case	Memory Size	FWFT Support	Function	Mounting Type	Supplier Device Package	Data Rate	Bus Directional	Expansion Type	Current - Supply (Max) [Max]
Renesas Electronics Corporation 72V3641L15PFG8			3 V	3.6 V	70 °C	0 °C	10 ns	120-LQFP	36 K		Synchronous	Surface Mount	120-TQFP (14x14)	66.7 MHz	Bi-Directional	Depth Width	400 µA

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Description

General part information

72V3641 Series

The 72V3641is a 1K x 36 Sync FIFO memory that is a 3.3V version of the 723641. It supports clock frequencies up to 67 MHz and has read access times as fast as 10ns. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. The FIFO operates in First Word Fall Through mode. Communication between each port may take place with two 36-bit mailbox registers. The enables for each port are arranged to provide a simple interface between microprocessors and/or buses with synchronous control.