
IS25LP512MG-JLLE
ActiveFLASH MEMORY, SERIAL NOR, 512 MBIT, 64M X 8BIT, SPI, WSON, 8 PINS
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IS25LP512MG-JLLE
ActiveFLASH MEMORY, SERIAL NOR, 512 MBIT, 64M X 8BIT, SPI, WSON, 8 PINS
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Technical Specifications
Parameters and characteristics for this part
| Specification | IS25LP512MG-JLLE |
|---|---|
| Access Time | 5.5 ns |
| Clock Frequency | 166 MHz |
| Memory Format | FLASH |
| Memory Interface | Quad I/O, QPI, SPI, DTR |
| Memory Organization | 64 M |
| Memory Size | 64 MB |
| Memory Type | Non-Volatile |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 105 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 8-WDFN Exposed Pad |
| Supplier Device Package | 8-WSON (8x6) |
| Technology | FLASH - NOR |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 2.3 V |
| Write Cycle Time - Word, Page [custom] | 1 ms |
| Write Cycle Time - Word, Page [custom] | 50 µs |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tray | 1 | $ 6.63 | |
| 10 | $ 6.05 | |||
| 25 | $ 5.94 | |||
| 40 | $ 5.90 | |||
| 80 | $ 5.29 | |||
| 230 | $ 5.27 | |||
| 480 | $ 4.94 | |||
| 960 | $ 4.73 | |||
Description
General part information
IS25LP512 Series
IS25LP512MG-JLLE is a 512Mb serial flash memory 166MHz multi I/O SPI and quad I/O QPI DTR interface. It offers a versatile storage solution with high flexibility and performance in a simplified pin count package. ISSI’s “Industry Standard Serial Interface” flash is for systems that require limited space, a low pin count, and low power consumption. The device is accessed through a 4-wire SPI interface consisting of a serial data input (SI), serial data output (SO), serial clock (SCK), and chip enable (CE#) pins, which can also be configured to serve as multi-I/O. The device supports dual and quad I/O as well as standard, dual output, and quad output SPI. This series of flash adds support for DTR (double transfer rate) commands that transfer addresses and read data on both edges of the clock. These transfer rates can outperform 16-bit parallel flash memories allowing for efficient memory access to support XIP (execute in place) operation.
Documents
Technical documentation and resources