Zenode.ai Logo
Beta
K
SNJ54ABT374J - 20-CDIP

SNJ54ABT374J

Active
Texas Instruments

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

Deep-Dive with AI

Search across all available documentation for this part.

SNJ54ABT374J - 20-CDIP

SNJ54ABT374J

Active
Texas Instruments

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

Technical Specifications

Parameters and characteristics for this part

SpecificationSNJ54ABT374J
Clock Frequency150 MHz
Current - Output High, Low [custom]24 mA
Current - Output High, Low [custom]48 mA
FunctionStandard
Input Capacitance3.5 pF
Max Propagation Delay @ V, Max CL6.6 ns
Mounting TypeThrough Hole
Number of Bits per Element8
Number of Elements1
Operating Temperature [Max]125 °C
Operating Temperature [Min]-55 °C
Output TypeTri-State, Non-Inverted
Package / Case20-CDIP
Supplier Device Package20-CDIP
Trigger TypePositive Edge
TypeD-Type
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]4.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
Texas InstrumentsTUBE 1$ 21.29
100$ 18.59
250$ 14.34
1000$ 12.82

Description

General part information

5962-9314901 Series

These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight flip-flops of the SN54ABT374 and SN74ABT374A are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.

A buffered output-enable () input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.