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54FCT373CTDB - 54FCT245TDB

54FCT373CTDB

Obsolete
Renesas Electronics Corporation

IC D-TYPE TRANSP 8:8 20-CDIP

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54FCT373CTDB - 54FCT245TDB

54FCT373CTDB

Obsolete
Renesas Electronics Corporation

IC D-TYPE TRANSP 8:8 20-CDIP

Deep-Dive with AI

DocumentsDatasheet

Technical Specifications

Parameters and characteristics for this part

Specification54FCT373CTDB
Circuit [custom]8
Circuit [custom]8
Delay Time - Propagation8 ns
Independent Circuits1
Logic TypeD-Type Transparent Latch
Mounting TypeThrough Hole
Operating Temperature [Max]125 °C
Operating Temperature [Min]-55 °C
Output TypeTri-State
Package / Case20-CDIP
Supplier Device Package20-CDIP
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]4.5 V

54FCT373T Series

NON-INVERTING OCTAL LATCH

PartLogic TypePackage / CaseIndependent CircuitsVoltage - Supply [Min]Voltage - Supply [Max]Supplier Device PackageOutput TypeDelay Time - PropagationMounting TypeOperating Temperature [Min]Operating Temperature [Max]Circuit [custom]Circuit [custom]
Renesas Electronics Corporation
D-Type Transparent Latch
20-LCC
1
4.5 V
5.5 V
20-LCC (8.89x8.89)
Tri-State
9.8 ns
Surface Mount
-55 °C
125 °C
8
8
Renesas Electronics Corporation
D-Type Transparent Latch
20-LCC
1
4.5 V
5.5 V
20-LCC (8.89x8.89)
Tri-State
8 ns
Surface Mount
-55 °C
125 °C
8
8
Renesas Electronics Corporation
D-Type Transparent Latch
20-CDIP
1
4.5 V
5.5 V
20-CDIP
Tri-State
8 ns
Through Hole
-55 °C
125 °C
8
8
Renesas Electronics Corporation
D-Type Transparent Latch
20-CDIP
1
4.5 V
5.5 V
20-CDIP
Tri-State
9.8 ns
Through Hole
-55 °C
125 °C
8
8
Renesas Electronics Corporation
D-Type Transparent Latch
20-CDIP
1
4.5 V
5.5 V
20-CDIP
Tri-State
15 ns
Through Hole
-55 °C
125 °C
8
8

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$

Description

General part information

54FCT373T Series

The IDT 54FCT373T is an octal transparent latch with 3-state outputs and is intended for bus oriented applications. The flip-flops appear transparent to the data when Latch Enable (LE) is high. When LE is low, the data that meets the set-up time is latched. The 54FCT373T operates at -55C to +125C. (For commercial version, see 74FCT373T)

Documents

Technical documentation and resources