71V547S100PFG8
Obsolete3.3V 128K X 36 ZBT SYNCHRONOUS FLOW-THROUGH SRAM
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71V547S100PFG8
Obsolete3.3V 128K X 36 ZBT SYNCHRONOUS FLOW-THROUGH SRAM
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Technical Specifications
Parameters and characteristics for this part
| Specification | 71V547S100PFG8 |
|---|---|
| Access Time | 10 ns |
| Memory Format | SRAM |
| Memory Interface | Parallel |
| Memory Organization | 128K x 36 |
| Memory Size | 4.5 Mbit |
| Memory Type | Volatile |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 70 °C |
| Operating Temperature [Min] | 0 °C |
| Package / Case | 100-LQFP |
| Supplier Device Package | 100-TQFP (14x14) |
| Technology | SRAM - Synchronous, SDR (ZBT) |
| Voltage - Supply [Max] | 3.465 V |
| Voltage - Supply [Min] | 3.135 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
Description
General part information
71V547 Series
The 71V547 3.3V CMOS SRAM is organized as 128K x 36 bits. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turn-around. The 71V547 contains address, data-in and control signal registers. The outputs are flow-through (no output data register). In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.
Documents
Technical documentation and resources