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5P49EE602NLGI - 24-VFQFPN

5P49EE602NLGI

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Renesas Electronics Corporation

VERSACLOCK LOW POWER CLOCK GENERATOR

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5P49EE602NLGI - 24-VFQFPN

5P49EE602NLGI

Active
Renesas Electronics Corporation

VERSACLOCK LOW POWER CLOCK GENERATOR

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

Specification5P49EE602NLGI
Differential - Input:OutputNo/Yes
Divider/MultiplierYes/No
Frequency - Max [Max]120 MHz
InputLVTTL, Crystal
Mounting TypeSurface Mount
Number of Circuits1
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
OutputLVCMOS, LVTTL
Package / Case24-VFQFN Exposed Pad
PLLYes with Bypass
Ratio - Input:Output2:5
Supplier Device Package24-QFN (4x4)
TypeClock Generator
Voltage - Supply [Max]3.465 V
Voltage - Supply [Min]1.71 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 490$ 3.39

Description

General part information

5P49EE602 Series

The 5P49EE602 is a programmable clock generator intended for low-power, battery-operated consumer applications. There are four internal PLLs, each individually programmable, allowing for up to six different output frequencies. The frequencies are generated from a single reference clock. The reference clock can come from either a TCXO or fundamental mode crystal. An additional 32.768kHz crystal oscillator is available to provide a real-time clock or non-critical performance MHz processor clock. The 5P49EE602 can be programmed through the use of the I2C interfaces. The programming interface enables the device to be programmed when it is in normal operation or what is commonly known as in-system programmable. An internal EEPROM allows the user to save and restore the configuration of the device without having to reprogram it on power-up. Each of the four PLLs has an 8-bit reference divider and an 11-bit feedback divider. This allows the user to generate four unique non-integer-related frequencies. The PLL loop bandwidth is programmable to allow the user to tailor the PLL response to the application. For instance, the user can tune the PLL parameters to minimize jitter generation or maximize jitter attenuation. Spread spectrum generation is supported on one of the PLLs. The device is specifically designed to work with display applications to ensure that the spread profile remains consistent for each HSYNC in order to reduce ROW noise. It also may operate in standard spread spectrum mode. There are a total of five 8-bit output dividers. The outputs are connected to the PLLs via the switch matrix. The switch matrix allows the user to route the PLL outputs to any output bank. This feature can be used to simplify and optimize the board layout. In addition, each output's slew rate and enable/disable function can be programmed.

Documents

Technical documentation and resources