5T907PAGI8
Obsolete2.5V SINGLE DATA RATE 1:10 CLOCK BUFFER TERABUFFER™
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5T907PAGI8
Obsolete2.5V SINGLE DATA RATE 1:10 CLOCK BUFFER TERABUFFER™
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | 5T907PAGI8 |
|---|---|
| Differential - Input:Output | Yes/No |
| Frequency - Max [Max] | 250 MHz |
| Input | HSTL, LVTTL, eHSTL, LVPECL |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output | eHSTL, HSTL, LVTTL |
| Package / Case | 48-TFSOP |
| Package / Case | 0.24 in |
| Package / Case [custom] | 6.1 mm |
| Ratio - Input:Output [custom] | 1:10 |
| Supplier Device Package | 48-TSSOP |
| Type | Fanout Buffer (Distribution) |
| Voltage - Supply [Max] | 2.6 V |
| Voltage - Supply [Min] | 2.4 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
Description
General part information
5T907 Series
The IDT5T907 2.5V single data rate (SDR) clock buffer is a user-selectable single-ended or differential input to ten single-ended outputs buffer built on advanced metal CMOS technology. The SDR clock buffer fanout from a single or differential input to ten single-ended outputs reduces the loading on the preceding driver and provides an efficient clock distribution network. The IDT5T907 can act as a translator from a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL, 1.8V/2.5V LVTTL outputs. Selectable interface is controlled by 3-level input signals that may be hard-wired to appropriate high-mid-low levels. The IDT5T907 has two output banks that can be asynchronously enabled/ disabled. Multiple power and grounds reduce noise.
Documents
Technical documentation and resources