XIO1100ZWS
ObsoletePHY 1-CH 1.5V/1.8V/3.3V 100-PIN BGA MICROSTAR TRAY
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XIO1100ZWS
ObsoletePHY 1-CH 1.5V/1.8V/3.3V 100-PIN BGA MICROSTAR TRAY
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Technical Specifications
Parameters and characteristics for this part
| Specification | XIO1100ZWS |
|---|---|
| Applications | PCI Express to PCI Translation Bridge |
| Interface | TI-PIPE |
| Mounting Type | Surface Mount |
| Package / Case | 100-LFBGA |
| Supplier Device Package | 100-NFBGA (12x12) |
| Voltage - Supply [Max] | 3.6 V, 1.65 V |
| Voltage - Supply [Min] | 1.35 V, 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Texas Instruments | JEDEC TRAY (5+1) | 1 | $ 10.69 | |
| 100 | $ 8.71 | |||
| 250 | $ 6.85 | |||
| 1000 | $ 5.81 | |||
Description
General part information
XIO1100 Series
The XIO1100 is a PCI Express. PHY that is compliant with PCI Express Base Specification Revision 1.1 and that interfaces the PCI Express Media Access Layer (MAC) to a PCI Express serial link by using a modified version of the interface described in PHY Interface for the PCI Express. Architecture (also known as PIPE interface) by Intel Corporation. This modified version of the PIPE interface is referred to as a TI-PIPE interface throughout this data manual.
The TI-PIPE interface is a pin-configurable interface that can be configured as either a 16-bit or an 8-bit interface.
The XIO1100 PHY interfaces to a 2.5 Gbps PCI Express serial link with a transmit differential pair (TXP and TXN) and a receive differential pair (RXP and RXN). Incoming data at the XIO1100 PHY receive differential pair (RXP and RXN) is forwarded to the MAC on the RXDATA output bus. Data received from the MAC on the TXDATA input bus is forwarded to the XIO1100 PHY transfer differential pair (TXP and TXN).
Documents
Technical documentation and resources