Catalog
Low-power Schmitt trigger inverter
Key Features
• Wide supply voltage range from 0.8 V to 3.6 V
• CMOS low power dissipation
• High noise immunity
• Overvoltage tolerant inputs to 3.6 V
• Low static power consumption; ICC= 0.9 μA (maximum)
• Latch-up performance exceeds 100 mA per JESD 78 Class II
• Low noise overshoot and undershoot < 10 % of VCC
• IOFFcircuitry provides partial Power-down mode operation
• Complies with JEDEC standards:
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
• Multiple package options
• Specified from -40 °C to +85 °C and -40 °C to +125 °C
Description
AI
The 74AUP1G14 is a single inverter with Schmitt-trigger input. This device ensures very low static and dynamic power consumption across the entire VCCrange from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFFcircuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.