5962-9759201 Series
Dual Positive-Edge-Triggered D-type Flip-Flops With Clear And Preset
Manufacturer: Texas Instruments
Catalog
Dual Positive-Edge-Triggered D-type Flip-Flops With Clear And Preset
| Part | Mounting Type | Output Type | Operating Temperature [Max] | Operating Temperature [Min] | Voltage - Supply [Min] | Voltage - Supply [Max] | Package / Case | Current - Output High, Low [custom] | Current - Output High, Low [custom] | Clock Frequency | Type | Number of Bits per Element | Supplier Device Package | Trigger Type | Current - Quiescent (Iq) | Number of Elements | Function |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments | Surface Mount | Complementary | 125 °C | -55 °C | 4.5 V | 5.5 V | 20-CLCC | 1 mA | 20 mA | 145 MHz | D-Type | 1 | 20-LCCC (8.89x8.89) | Positive Edge | 16 mA | 2 | Reset Set(Preset) |
Texas Instruments | Surface Mount | Complementary | 125 °C | -55 °C | 4.5 V | 5.5 V | 14-CFlatpack | 1 mA | 20 mA | 145 MHz | D-Type | 1 | Positive Edge | 16 mA | 2 | Reset Set(Preset) | |
Texas Instruments | Through Hole | Complementary | 125 °C | -55 °C | 4.5 V | 5.5 V | 14-CDIP | 1 mA | 20 mA | 145 MHz | D-Type | 1 | 14-CDIP | Positive Edge | 16 mA | 2 | Reset Set(Preset) |
Texas Instruments | Surface Mount | Complementary | 125 °C | -55 °C | 4.5 V | 5.5 V | 20-CLCC | 1 mA | 20 mA | 145 MHz | D-Type | 1 | 20-LCCC (8.89x8.89) | Positive Edge | 16 mA | 2 | Reset Set(Preset) |
Texas Instruments |
Key Features
• Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPsPackage Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs
Description
AI
These devices contain two independent positive-edge-triggered D-type flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. Whenandare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.
The SN54F74 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F74 is characterized for operation from 0°C to 70°C.
The output levels are not guaranteed to meet the minimum levels for VOH. Furthermore, this configuration is nonstable; that is, it will not persist whenorreturns to its inactive (high) level.
These devices contain two independent positive-edge-triggered D-type flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. Whenandare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.
The SN54F74 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F74 is characterized for operation from 0°C to 70°C.
The output levels are not guaranteed to meet the minimum levels for VOH. Furthermore, this configuration is nonstable; that is, it will not persist whenorreturns to its inactive (high) level.