UCC27532-Q1 Series
2.5-A/5-A single-channel gate driver with 8-V UVLO, 35-V VDD, CMOS inputs, and split outputs
Manufacturer: Texas Instruments
Catalog
2.5-A/5-A single-channel gate driver with 8-V UVLO, 35-V VDD, CMOS inputs, and split outputs
Key Features
• Qualified for automotive applicationsAEC-Q100 qualified with the following results:Device temperature grade 1Low-cost gate driver (offering optimal solution for driving FET and IGBTs)Superior replacement to discrete transistor pair drive (providing easy interface with controller)CMOS compatible input-logic threshold (becomes fixed at VDD above 18V)Split outputs allow separate turnon and turnoff tuningEnable with Fixed TTL compatible thresholdHigh 2.5A source and 5A sink peak-drive currents at 18V VDDWide VDD range from 10V up to 35VInput pins capable of withstanding up to –5V DC below groundOutput held low when inputs are floating or during VDD UVLOFast propagation delays (17ns typical)Fast rise and fall times (15ns and 7ns typical with 1800pF load)Undervoltage lockout (UVLO)Used as a high-side or low-side driver (if designed with proper bias and signal isolation)Low-cost space-saving 6-pin DBV (SOT-23) packageOperating temperature range of –40°C to 140°CQualified for automotive applicationsAEC-Q100 qualified with the following results:Device temperature grade 1Low-cost gate driver (offering optimal solution for driving FET and IGBTs)Superior replacement to discrete transistor pair drive (providing easy interface with controller)CMOS compatible input-logic threshold (becomes fixed at VDD above 18V)Split outputs allow separate turnon and turnoff tuningEnable with Fixed TTL compatible thresholdHigh 2.5A source and 5A sink peak-drive currents at 18V VDDWide VDD range from 10V up to 35VInput pins capable of withstanding up to –5V DC below groundOutput held low when inputs are floating or during VDD UVLOFast propagation delays (17ns typical)Fast rise and fall times (15ns and 7ns typical with 1800pF load)Undervoltage lockout (UVLO)Used as a high-side or low-side driver (if designed with proper bias and signal isolation)Low-cost space-saving 6-pin DBV (SOT-23) packageOperating temperature range of –40°C to 140°C
Description
AI
The UCC27532-Q1 device is a single-channel high-speed gate driver capable of effectively driving MOSFET and IGBT power switches by up to 2.5A source and 5A sink (asymmetrical drive) peak current. Strong sink capability in asymmetrical drive boosts immunity against parasitic Miller turnon effect. The UCC27532-Q1 device also features a split-output configuration where the gate-drive current is sourced through the OUTH pin and sunk through the OUTL pin. This pin arrangement allows the user to apply independent turnon and turnoff resistors to the OUTH and OUTL pins respectively and easily control the switching slew rates.
The driver has rail-to-rail drive capability and an extremely-small propagation delay of 17ns (typically).
The UCC27532-Q1 device has a CMOS-input threshold-centered 55% rise and 45% fall in regards of VDD at VDD below or equal 18V. When VDD is above 18V, the input threshold remains fixed at the maximum level.
The driver has an EN pin with a fixed TTL-compatible threshold. EN is internally pulled up; pulling EN low disables driver, while leaving it open provides normal operation. The EN pin can be used as an additional input with the same performance as the IN pin.
Leaving the input pin of driver open holds the output low. The logic behavior of the driver is shown in the Timing Diagram, Input/Output Logic Truth Table, and .
Internal circuitry on the VDD pin provides an undervoltage-lockout function that holds the output low until the VDD supply voltage is within operating range.
The UCC27532-Q1 driver is offered in a 6-pin standard SOT-23 (DBV) package. The device operates over a wide temperature range of –40°C to 140°C.
The UCC27532-Q1 device is a single-channel high-speed gate driver capable of effectively driving MOSFET and IGBT power switches by up to 2.5A source and 5A sink (asymmetrical drive) peak current. Strong sink capability in asymmetrical drive boosts immunity against parasitic Miller turnon effect. The UCC27532-Q1 device also features a split-output configuration where the gate-drive current is sourced through the OUTH pin and sunk through the OUTL pin. This pin arrangement allows the user to apply independent turnon and turnoff resistors to the OUTH and OUTL pins respectively and easily control the switching slew rates.
The driver has rail-to-rail drive capability and an extremely-small propagation delay of 17ns (typically).
The UCC27532-Q1 device has a CMOS-input threshold-centered 55% rise and 45% fall in regards of VDD at VDD below or equal 18V. When VDD is above 18V, the input threshold remains fixed at the maximum level.
The driver has an EN pin with a fixed TTL-compatible threshold. EN is internally pulled up; pulling EN low disables driver, while leaving it open provides normal operation. The EN pin can be used as an additional input with the same performance as the IN pin.
Leaving the input pin of driver open holds the output low. The logic behavior of the driver is shown in the Timing Diagram, Input/Output Logic Truth Table, and .
Internal circuitry on the VDD pin provides an undervoltage-lockout function that holds the output low until the VDD supply voltage is within operating range.
The UCC27532-Q1 driver is offered in a 6-pin standard SOT-23 (DBV) package. The device operates over a wide temperature range of –40°C to 140°C.